Circuit and method for providing a fail-safe differential receiver
View Patent ↗A fail-safe differential receiver having a differential amplifier adapted to receive first and second differential input signals and generate a differential voltage. A peak detector is coupled to the differential amplifier for generating a detect signal and a comparator is coupled to the peak detector for comparing the detect signal to a threshold voltage and providing a comparison signal. A directing circuit is coupled to the differential amplifier for receiving the first and second differential input signals and is coupled to the comparator for receiving the comparison signal. An output amplifier is coupled to the directing circuit. The directing circuit selectively directs the first and second differential input signals to the output amplifier as a function of the value of the comparison signal from the comparator.
1. A fail-safe differential receiver circuit for use with a first differential input signal and a second differential input signal and at least one predetermined signal and a threshold voltage, the circuit comprising a differential amplifier configured to receive the first and second differential input signals, the differential amplifier generating first and second differential signals that are based on the first and second differential input signals and have a differential voltage, a peak detector coupled to the differential amplifier for generating a detect signal, a comparator coupled to the peak detector for comparing the detect signal to the threshold voltage and providing a comparison signal, and a directing circuit coupled to the differential amplifier for receiving the generated first and second differential signals and coupled to the comparator for receiving the comparison signal, the directing circuit selectively directing between the generated first and second differential signals and the at least one predetermined signal as a function of the value of the comparison signal from the comparator.
2. The fail-safe differential receiver circuit of claim 1 , wherein the differential amplifier comprises a first transistor for receiving the first differential input signal and a second transistor for receiving the second differential input signal.
3. The fail-safe differential receiver circuit of claim 2 , further comprising a first current source coupled to the first and second transistors.
4. The fail-safe differential receiver circuit of claim 3 , further comprising a second current source and a resistor coupled to the second current source for providing the threshold voltage.
5. The fail-safe differential receiver circuit of claim 4 , further comprising a third transistor coupled to the resistor and the second current source.
6. The fail-safe differential receiver circuit of claim 5 , wherein the peak detector includes a fourth transistor coupled to the first transistor and a fifth transistor coupled to the second transistor.
7. The fail-safe differential receiver of claim 6 , further comprising a third current source coupled to the fourth and fifth transistors.
8. The fail-safe differential receiver circuit of claim 7 , wherein the comparator includes a sixth transistor coupled to the third, fourth, and fifth transistors.
9. The fail-safe differential receiver of claim 8 , wherein the directing circuit includes a latch.
10. The fail-safe differential receiver circuit of claim 9 , wherein the latch includes a seventh transistor and an eighth transistor coupled to the sixth transistor.
11. The fail-safe differential receiver circuit of claim 10 , further comprising a ninth transistor and a tenth transistor coupled to the seventh and the eighth transistors.
12. The fail-safe differential receiver circuit of claim 11 , wherein the ninth transistor is coupled to the first transistor and the tenth transistor is coupled to the second transistor.
13. The fail-safe differential receiver circuit of claim 12 , wherein the ninth and tenth transistors are coupled to an output of the circuit.
14. The fail-safe differential receiver circuit of claim 1 , wherein the peak detector includes an integrating capacitor.
15. The fail-safe differential receiver circuit of claim 9 for use with first and second earlier differential signals, wherein the latch includes a memory for retaining the first and second earlier differential signals and wherein the latch directs the first and second differential signals when the comparison signal is a first value and retains the first and second earlier differential signals as the at least one predetermined signal when the comparison signal is a second value.
16. The fail-safe differential receiver of claim 1 , wherein the directing circuit comprises a combination of logic gates for directing a high or low voltage signal as the at least one predetermined signal when the comparison signal is a second value.
17. A fail-safe differential receiver circuit for use with a first differential input signal and a second differential input signal and at least one predetermined signal and a threshold voltage, the circuit comprising a first transistor coupled to the first differential input signal and a second transistor coupled to the second differential input signal for generating first and second differential signals that are based on the first and second differential input signals and have a differential voltage, a resistor coupled to a first current source for setting a threshold voltage, a third transistor coupled to the resistor and the first current source, a comparator coupled to the first, second, and third transistors for comparing the differential voltage to the threshold voltage and generating a comparison signal, and a fourth transistor and a fifth transistor coupled to the comparator for forming a directing circuit, the directing circuit selectively directing between the first and second differential signals and the at least one predetermined signal as a function of the value of the comparison signal from the comparator.
18. The fail-safe differential receiver circuit of claim 17 , further comprising a peak detector coupled to the first and second transistors.
19. The fail-safe differential receiver circuit of claim 18 , wherein the peak detector includes a sixth transistor coupled to the first transistor and a seventh transistor coupled to the second transistor.
20. The fail-safe differential receiver circuit of claim 19 , wherein the comparator includes an eighth transistor coupled to the sixth and seventh transistors.
21. The fail-safe differential receiver circuit of claim 17 , wherein the fourth and fifth transistors are coupled to a ninth transistor and a tenth transistor.
22. The fail-safe differential receiver circuit of claim 21 , wherein the ninth transistor is coupled to the first transistor and the tenth transistor is coupled to the second transistor.
23. The fail-safe differential receiver of claim 22 , wherein the ninth and tenth transistors are coupled to an output of the receiver.
24. The fail-safe differential receiver of claim 18 , wherein the peak detector further includes an integrating capacitor.
25. The fail-safe differential receiver of claim 17 , wherein the directing circuit comprises a latch.
26. The fail-safe differential receiver of claim 17 , wherein the directing circuit comprises a combination of logic gates for directing a high or low voltage signal as the at least one predetermined signal when the comparison signal indicates that the differential voltage is lower than the threshold voltage.
27. A method for providing a fail-safe differential receiver, the method comprising generating a peak voltage signal amplitude from first and second differential signals that are based on a first differential input signal and a second differential input signal, comparing the peak voltage signal amplitude to a threshold voltage to generate a comparison signal and providing the comparison signal to a directing circuit, the directing circuit selectively directing between the first and second differential signals and at least one predetermined signal as a function of the comparison signal.
28. The method of claim 27 , further comprising generating the threshold voltage with a resistor coupled to a current source.
29. The method of claim 27 , further comprising determining the peak voltage signal amplitude with a peak detector.
30. The method of claim 28 , wherein comparing the peak voltage signal amplitude to the threshold voltage includes using a comparator coupled to the peak detector.
31. The method of claim 27 , wherein selectively directing includes enabling the directing circuit with the comparison signal when the generated peak voltage signal amplitude is higher than the threshold voltage.
32. The method of claim 27 , wherein selectively directing includes disabling the directing circuit with the comparison signal when the generated peak voltage signal amplitude is smaller than the threshold voltage.
33. The method of claim 27 , wherein the comparison signal is provided to a combination of logic gates for directing a high or low voltage signal as the at least one predetermined signal when the comparison signal indicates that the generated peak voltage signal amplitude is lower than the threshold voltage.