Solid-state memory device with protection against power failure
View Patent ↗A data preservation system for flash memory systems with a host system, the flash memory system receiving a host system power supply and energizing an auxiliary energy store therewith and communicating with the host system via an interface bus, wherein, upon loss of the host system power supply, the flash memory system actively isolates the connection to the host system power supply and isolates the interface bus and employs the supplemental energy store to continue write operations to flash memory.
1. A storage system comprising:
a controller that writes data to, and reads data from, a non-volatile storage medium;
an auxiliary power source that receives a power signal from a host system, and generates a regulated power signal that is provided to the controller, wherein the auxiliary power source is capable of maintaining the regulated power signal to the controller when the power signal from the host system is interrupted, such that the auxiliary power source acts as a backup power supply when power from the host system is interrupted; and
a voltage detection circuit that monitors the power signal from the host system and upon detecting a voltage drop in the power signal, blocking the host system from performing write operations to the storage system.
2. The storage system of claim 1 , further comprising a capacitive device that acts as an additional source of backup power to the controller, wherein the capacitive device is coupled to the auxiliary power source such that the capacitive device is charged when power is supplied by the host system.
3. The storage system of claim 1 , wherein the non-volatile storage medium comprises flash memory.
4. The storage system of claim 1 , wherein the non-volatile storage medium comprises a flash memory card.
5. The storage system of claim 1 , wherein the auxiliary power source and the voltage detection circuit are integrated within the same circuit.
6. The storage system of claim 1 , wherein the auxiliary power source is a charge pump circuit.
7. The storage system of claim 1 , wherein the auxiliary power source is responsive to the termination of the power signal from the host system by providing power to the controller for at least the time period needed to complete all outstanding operations.
8. The storage system of claim 1 , wherein the auxiliary power source is responsive to the termination of the power signal from the host system by providing power to the controller for at least the time period needed to, at least, complete an outstanding write operation.
9. A method of responding to a voltage reduction in a power signal provided by a host system to a storage system, the method comprising:
receiving the power signal from the host system, wherein the host system is separate from and connectable to the storage system;
detecting the voltage reduction in the power signal with a detection circuit of the storage system;
after the voltage reduction is detected, inhibiting the host system from writing data to the storage system; and
after the voltage reduction is detected, providing power to a controller of the storage system from at least one source of backup power contained with the storage system, to allow the storage system to complete operations that were in progress when the voltage reduction was detected.
10. The method of claim 9 , wherein the at least one source of backup power comprises a capacitive device.
11. The method of claim 9 , wherein the at least one source of backup power comprises a charge pump circuit.
12. The method of claim 9 , wherein the step of providing power to a controller of the storage system is performed for a sufficient time period so that the storage system completes all outstanding operations.
13. The method of claim 9 , wherein the storage system is a solid-state non-volatile memory card.
14. A solid-state memory system comprising:
a solid-state non-volatile memory array;
a controller that writes data to, and reads data from, the solid-state non-volatile memory array in response to operations initiated by a host system;
a power regulation circuit that receives a power signal from the host system and generates a regulated power signal that is provided to the controller, where the power regulation circuit is capable of maintaining the regulated power signal to the controller when the power signal from the host system is interrupted, such that the power regulation circuit acts as a backup power supply when power from the host system is interrupted;
a voltage detection circuit that monitors the power signal from the host system to detect voltage reduction therein; and
an isolation circuit for isolating the solid-state memory system from the host system upon the voltage reduction circuit detecting the voltage reduction.
15. The solid-state memory system of claim 14 , wherein the solid-state non-volatile memory array comprises flash memory.
16. The solid-state memory system of claim 14 is a flash memory card.
17. The solid-state memory system of claim 14 , wherein the power regulation circuit comprises a capacitive device.
18. The solid-state memory system of claim 14 , wherein the power regulation circuit comprises a charge pump circuit.
19. The solid-state memory system of claim 14 , wherein the power regulation circuit is further configured to complete the outstanding operations of the controller after power from the host system is interrupted.
20. The solid-state memory system of claim 14 , wherein the power regulation circuit is further configured to complete at least one outstanding write operation of the controller after power from the host system is interrupted.