Method for forming a DRAM semiconductor device with a sense amplifier
View Patent ↗A method for forming a sense amplifier of a semiconductor device prevents bit lines from being bridged to each other by a stepped portion created on an insulation interlayer due to irregular density of a P-type impurity, which is ion-implanted into an insulation interlayer in a P+ pickup region when a sense amplifier of a semiconductor device is formed. Yield ratio of semiconductor devices is improved.
1. A method for forming a sense amplifier of a semiconductor device comprising the steps of:
providing a semiconductor substrate having an NMOS and a PMOS for a sense amplifier formed on the substrate, a P+ pickup and an N+ pickup formed on the substrate between the NMOS and the PMOS in the shape of parallel bars, and an insulation layer formed on the substrate between the NMOS and the P+ pickup, between the P+ pickup and the N+ pickup, and between the N+ pickup and the PMOS so that a portion of the insulation layer formed between the P+ pickup and the N+ pickup is bridged to a portion of the insulation layer formed in other regions;
forming an insulation interlayer on the insulation layer so as to cover the NMOS, the PMOS, the P+ pickup, and the N+ pickup;
etching the insulation interlayer so as to form contact holes for exposing a junction region of the NMOS, a junction region of the PMOS, the P+ pickup, the N+ pickup, and gates, respectively;
forming a mask pattern on the substrate, the contact holes being formed on the substrate, the mask pattern having hole-type openings for selectively exposing the contact holes in the junction region of the PMOS and in a region of the P+ pickup;
performing ion implantation of a P-type impurity in the junction region of the PMOS exposed by the contact holes and in the region of the P+ pickup exposed by the contact holes by using the mask pattern as an ion implantation barrier;
removing the mask pattern;
cleaning the substrate, the mask pattern having been removed from the substrate; and
forming bit lines on the insulation interlayer so as to fill the contact holes.
2. The method as claimed in claim 1 , wherein the mask pattern having hole-type openings is formed by using ArF exposure equipment.
3. A semiconductor device having a sense amplifier, the semiconductor device comprising:
a semiconductor substrate having an NMOS and a PMOS for a sense amplifier formed on the substrate, a P+ pickup and an N+ pickup formed on the substrate between the NMOS and the PMOS in the shape of parallel bars, and an insulation layer formed on the substrate between the NMOS and the P+ pickup, between the P+ pickup and the N+ pickup, and between the N+ pickup and the PMOS so that a portion of the insulation layer formed between the P+ pickup and the N+ pickup is bridged to a portion of the insulation layer formed in other regions;
an insulation interlayer formed on the insulation layer, said insulation layer covering the NMOS, the PMOS, the P+ pickup, and the N+ pickup;
contact holes etched into the insulation interlayer that expose a junction region of the NMOS, a junction region of the PMOS, the P+ pickup, the N+ pickup, and gates, respectively;
P-type impurities implanted in the junction region of the PMOS exposed by the contact holes and in the region of the P+ pickup exposed by the contact holes; and
bit lines formed on the insulation interlayer so as to fill the contact holes.
4. The semiconductor device of claim 3 wherein impurities are implanted using a mask pattern as an ion implantation barrier.