Nano tube cell, and semiconductor device having nano tube cell and double bit line sensing structure

1. A semiconductor device, comprising:

a plurality of top sub cell arrays and a plurality of bottom sub cell arrays having a plurality of main bit lines and a plurality of sub bit lines, by controlling an amount of a current supplied from a power voltage to the main bit line according to a sensing voltage of a sub bit line receiving a cell data;

a main bit line sense amplifier disposed between the plurality of top sub cell arrays and the plurality of bottom sub cell arrays, for sensing and amplifying a voltage of a top main bit line shared by the plurality of top sub cell arrays and a voltage of a bottom main bit line shared by the plurality of bottom sub cell arrays according to a sensing signal; and

word line drivers for selectively enabling word lines of the sub cell arrays for the read and write operation of the cell data,

wherein each of the sub cell arrays includes a plurality of memory cells wherein each of the plurality of memory cells includes a capacitor and a switch device selectively turned on/off according to a voltage difference between one side terminal of the capacitor and the sub bit line is coupled between the word line and the sub bit line,

wherein the switch device comprises:

a first PNPN tube turned on when the voltage of the sub bit line is higher than that of the one side electrode of the capacitor by a predetermined level, for enabling the current to flow from the sub bit line to the capacitor; and

a second PNPN tube turned on when the voltage of the one side electrode of the capacitor is higher than that of the bit line by a predetermined level, for enabling the current to flow from the capacitor to the bit line.

2. The semiconductor device of claim 1 , wherein the main bit line and the sub bit line maintain a ground voltage state before the word line is enabled, for reading or writing the cell data.

3. The semiconductor device of claim 1 , wherein a plurality of sub bitlines adjacent to one main bit line in left and right sides correspond to the one main bit line.

4. The semiconductor device of claim 3 , wherein the main bit line and the sub bit line maintain a ground voltage state before the word line is enabled, for reading or writing the cell data.

5. The semiconductor device of claim 3 , wherein each of the sub cell arrays has a folded bit line structure where a plurality of cells coupled to the plurality of sub bit lines adjacent to the main bit line do not share the word line.

6. The semiconductor device of claim 1 , wherein the first PNPN tube is a PNPN diode coupled between the second electrode and the bit line in the backward, and

wherein the second PNPN tube is a PNPN diode coupled between the second electrode and the bit line in the forward directions.

7. The semiconductor device of claim 6 , wherein the second PNPN diodes composing the first PNPN tube and the second PNPN tube are connected in series in the orthogonal direction to the word line.

8. The semiconductor device of claim 7 , wherein the capacitor is formed in a cross region of the serial PNPN tube chain and the word line.