High speed signal transmission line having reduced thickness regions
View Patent ↗Apparatus and associated systems and methods may include one or more features for high speed transmission line structures that may substantially reduce signal degradation due to effects, such as dielectric loss, parasitic capacitance, cross-talk, and/or reflections. For example, one such feature may include a dielectric layer having a reduced thickness within at least a part of a region that extends between two conductors fabricated on a PCB (printed circuit board). In some embodiments, the dielectric layer may include a solder mask layer that is partially or substantially absent in the region between two coplanar conductors. In another embodiment, a substrate layer made of a dielectric material may include a trench in the region between the two conductors. Another such feature, for example, may include a conductor having vias spaced less than a quarter wavelength apart to substantially reduce resonance effects on propagating high frequency signals.
1. A waveform processing system comprising:
a substantially planar substrate layer comprising a first dielectric material;
a first conductor and a second conductor disposed on the substrate layer;
a dielectric layer comprising a second dielectric material disposed on the first and second conductors and having a first thickness,; wherein the second dielectric material comprises a solder mask material; and
a region between the first and second conductors, wherein the dielectric layer has a second thickness in the region, and the second thickness is substantially less than the first thickness, and wherein a thickness of the substrate layer in the region between the first and second conductors is substantially less than a thickness of the substrate layer under one of the conductors.
2. The system of claim 1 , wherein one of the conductors comprises a plurality of vias connecting the conductor to a reference conductor in another planar layer, wherein each via is separated from at least one of the other vias by no more than one quarter wavelength for a propagating signal within a desired bandwidth.
3. The system of claim 1 , wherein the region extends from the first conductor to the second conductor.
4. The system of claim 1 , wherein the second thickness of the dielectric layer is of zero thickness in the region between the first and the second conductors.
5. The system of claim 1 , wherein the first dielectric material comprises FR-4.
6. The system of claim 1 , wherein the first and second conductors are substantially coplanar.
7. The system of claim 1 , wherein the first and second conductors comprise a high frequency transmission line.
8. The system of claim 7 , wherein dielectric loss is substantially reduced for a high frequency signal propagating along the transmission line.
9. The system of claim 1 , further comprising a third conductor disposed on the substrate, the dielectric layer further disposed over the third conductor, and a second region between the third and second conductors, wherein the dielectric layer has a third thickness in the region, and the third thickness is substantially less than the first thickness.
10. The system of claim 9 , wherein a thickness of the substrate layer in the second region is substantially less than a thickness of the substrate layer under one of the conductors.
11. A waveform processing system obtainable by performing steps comprising:
depositing a pair of adjacent conductors on a substantially planar substrate layer;
depositing a dielectric layer over the conductors and the planar substrate;
reducing a thickness of the substrate layer in the region between the adjacent pair of conductors, wherein the reduced thickness of the substrate layer is substantially less than a thickness of the substrate layer under one of the conductors; and
reducing a thickness of the deposited dielectric layer in a region between the adjacent pair of conductors so as to reduce capacitance between the adjacent pair of conductors, wherein the step of reducing the thickness of the substrate layer comprises performing a chemical etch.
12. A waveform processing system obtainable by performing steps comprising:
depositing a pair of adjacent conductors on a substantially planar substrate layer;
depositing a dielectric layer over the conductors and the planar substrate layer;
reducing a thickness of the substrate layer in the region between the adjacent pair of conductors, wherein the reduced thickness of the substrate layer is substantially less than a thickness of the substrate layer under one of the conductors; and
reducing a thickness of the deposited dielectric layer in a region between the adjacent pair of conductors so as to reduce capacitance between the adjacent pair of conductors, wherein the step of reducing the thickness of the dielectric layer comprises removing substantially all of the deposited dielectric from region.
13. The system of claim 12 , wherein the step of reducing the thickness of the substrate layer comprises performing a reactive ion etch.
14. The system of claim 12 , wherein the dielectric layer comprises a solder mask layer.
15. The system of claim 12 , wherein the region extends from one of the adjacent pair of conductors to the other of the adjacent pair of conductors.
16. The system of claim 12 , wherein the step of reducing the thickness of the deposited dielectric layer comprises performing a chemical etch.
17. The system of claim 12 , wherein the step of reducing the thickness of the deposited dielectric layer comprises performing a reactive ion etch.