IP Library Granted Patent US 7,332,420
Granted Patent B2
US 7,332,420 · App. 11/517,264 · Granted Feb 19, 2008

Method for manufacturing semiconductor device

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Quick Facts
Patent No.
US 7,332,420
App. No.
11/517,264
Granted
Feb 19, 2008
Kind
B2
Abstract

A method for manufacturing a semiconductor device having a P-type MOSFET and an N-type MOSFET, the method comprising the steps of: forming a gate insulating film, a non-doped polysilicon film, a metal silicide film, a metal nitride film and a metal film on a semiconductor substrate; processing at least the metal film, the metal nitride film and the metal silicide film to pattern them into the shape of a gate such that the portion of the meal silicide film that forms part of a gate electrode of a P-type MOSFET and the portion of the meal silicide film that forms part of a gate electrode of an N-type MOSFET are separated from each other; introducing P-type and N-type impurities into the respective regions of the non-doped polysilicon film where the P-type and N-type MOSFETs are formed; performing thermal treatment to diffuse the impurities; and patterning the polysilicon film with the impurities introduced into the shape of the gate.

Claims (29)

1. A method for manufacturing a semiconductor device with a P-type MOSFET and an N-type MOSFET, each comprising a gate electrode having a stacked structure in which a polysilicon film into which an impurity is introduced, a metal silicide film, a metal nitride film and a metal film are stacked on a gate insulating film in this order, the method comprising the steps of:

forming a gate insulating film on a semiconductor substrate;

forming a non-doped polysilicon film on the gate insulating film;

forming a metal silicide film on the non-doped polysilicon film;

forming a metal nitride film on the metal silicide film;

forming a metal film on the metal nitride film;

processing at least the metal film, the metal nitride film and the metal silicide film to pattern them into the shape of a gate such that the portion of the metal silicide film that forms part of a gate electrode of a P-type MOSFET and the portion of the metal silicide film that forms part of a gate electrode of an N-type MOSFET are separated from each other;

introducing a P-type impurity into the non-doped polysilicon film in the region where the P-type MOSFET is formed;

introducing an N-type impurity into the non-doped polysilicon film in the region where the N-type MOSFET is formed;

performing thermal treatment to diffuse the P-type and N-type impurities introduced in the polysilicon film; and

patterning the polysilicon film with the impurities introduced into the shape of the gate to form the gate electrodes.

2. The method for manufacturing a semiconductor device according to claim 1 , wherein when the metal film, the metal nitride film and the metal silicide film are processed, the upper portion of the non-doped polysilicon film is also processed and patterned into the shape of a gate.

3. The method for manufacturing a semiconductor device according to claim 1 , wherein the introduction of the P-type and N-type impurities are carried out by ion implantation.

4. The method for manufacturing a semiconductor device according to claim 3 , wherein the introduction of the P-type and N-type impurities are carried out by oblique ion implantation.

5. The method for manufacturing a semiconductor device according to claim 3 , wherein

the introduction of the P-type impurity is carried out by oblique ion implantation while the region where the N-type MOSFET is formed is masked, so that the P-type impurity is introduced into the portion of the polysilicon film that forms part of the gate electrode of the P-type MOSFET,

the introduction of the N-type impurity is carried out by oblique ion implantation while the region where the P-type MOSFET is formed is masked, so that the N-type impurity is introduced into the portion of the polysilicon film that forms part of the gate electrode of the N-type MOSFET, and

the thermal treatment diffuses the impurities throughout the portions of the polysilicon film that form part of the respective gate electrodes of the P-type MOSFET and the N-type MOSFET to achieve uniform concentration distribution of the impurities.

6. A method for manufacturing a semiconductor device with a P-type MOSFET and an N-type MOSFET, each comprising a gate electrode having a stacked structure in which a polysilicon film into which an impurity is introduced, a metal silicide film, a metal nitride film and a metal film are stacked on a gate insulating film in this order, the method comprising the steps of:

forming a gate insulating film on a semiconductor substrate;

forming a non-doped polysilicon film on the gate insulating film;

forming a metal silicide film on the non-doped polysilicon film;

forming a metal nitride film on the metal silicide film;

forming a metal film on the metal nitride film;

patterning the metal film, the metal nitride film, the metal silicide film and the upper portion of the non-doped polysilicon film into the shape of a gate;

introducing a P-type impurity into the non-doped polysilicon film in the region where a P-type MOSFET is formed;

introducing an N-type impurity into the non-doped polysilicon film in the region where an N-type MOSFET is formed;

performing thermal treatment to diffuse the P-type and N-type impurities introduced in the polysilicon film; and

patterning the polysilicon film with the impurities introduced into the shape of the gate to form the gate electrodes.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 9, 2014
From: ELPIDA MEMORY, INC.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 032645/0422 →