System and method for I/O ESD protection with floating and/or biased polysilicon regions
A system and method for electrostatic discharge protection. The system includes a plurality of transistors. The plurality of transistors includes a plurality of gate regions, a plurality of source regions, and a plurality of drain regions. The plurality of source regions and the plurality of drain regions are located within an active area in a substrate, and the active area is adjacent to at least an isolation region in the substrate. Additionally, the system includes a polysilicon region. The polysilicon region is separated from the substrate by a dielectric layer, and the polysilicon region intersects each of the plurality of gate regions. At least a part of the polysilicon region is on the active area.
1. A system for electrostatic discharge protection, the system comprising:
a plurality of transistors, the plurality of transistors including a plurality of gate electrodes formed in parallel, a plurality of source regions, and a plurality of drain regions, the plurality of source regions and the plurality of drain regions being located within an active area in a substrate, the active area being adjacent to at least an isolation region in the substrate; and
a polysilicon region, the polysilicon region not being part of the gate regions and completely enclosing the plurality of source and drain regions in a top view, and separated from the substrate by a dielectric layer;
wherein a first part of the polysilicon region intersects each of the plurality of gate regions at two distal ends, each of the gate electrodes having a first side associated with one of the source regions extending continuously along the first side between the two distal ends and a second side associated with one of the drain regions extending continuously along the second side between the two distal ends,
wherein the plurality of gate electrodes is not mesh-shaped or grid-shaped;
wherein each one of the source regions comprises at least a source contact;
wherein each one of the drain regions comprises at least a drain contact;
wherein a second part of the polysilicon region on the active area is disposed along an inner peripheral edge of the active area, the inner peripheral edge of the active area being adjacent to the at least an isolation region,
wherein the second part of the polysilicon region on the active area does not intersect the plurality of gate electrodes.
2. The system of claim 1 wherein the active area is surrounded by at least the isolation region in the substrate, the isolation region being one of a shallow trench isolation region and a field oxide region.
3. The system of claim 1 wherein:
the polysilicon region is electrically connected to each of the plurality of gate electrodes and the polysilicon region is maintained at substantially the same potential as each of the plurality of gate electrodes.
4. The system of claim 1 wherein the polysilicon region is at least partially overlying the active area.
5. The system of claim 1 wherein the plurality of source regions and the plurality of drain regions comprise N+ regions.
6. The system of claim 5 wherein the substrate comprises two LDD regions for each of the N+ regions.
7. The system of claim 1 wherein the substrate comprises a p-well.
8. The system of claim 6 wherein the two LDD regions for a corresponding N+ region are in direct contact with the corresponding N+ region.
9. The system of claim 6 wherein the two LDD regions comprise a pocket implant region and a first LDD region.
10. The system of claim 9 wherein pocket implant region is p-type doped.
11. The system of claim 9 wherein the first LDD region is n-type doped.
12. The system of claim 1 wherein the plurality of transistors comprises input/output (I/O) transistors.