IP Library Granted Patent US 8,649,993
Granted Patent B1
US 8,649,993 · App. 11/520,202 · Granted Feb 11, 2014

Multi-domain execution of tests on electronic devices

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Quick Facts
Patent No.
US 8,649,993
App. No.
11/520,202
Granted
Feb 11, 2014
Kind
B1
Abstract

A device under test is divided into multiple test domains, and test conditions for each of the multiple test domains are defined separately, so that each test domain has its own test pattern, timing data, and other test conditions. Each test domain can start and stop independently, and run at different speeds. Further, triggers are used to specify how the tests executed in the different test domains interact and communicate with one another. Any test domain can generate or wait for a trigger from any other test domain. A test domain can wait for a trigger from a test domain in a CPU.

Claims (42)

1. A method of testing an electronic device using multiple test instruments and multiple test domains, said method comprising:

(a) initiating a test for a first test domain at a first instrument;

(b) generating a trigger at said first instrument in response to an event associated with said first test domain; and

(c) initiating a test for a second test domain at a second instrument in response to a receipt of said trigger at said second instrument,

wherein termination of said test for said first test domain is conditioned on an event in said second test domain.

2. A method as described in claim 1 , wherein said initiating a test for said first test domain further comprises executing a test pattern to generate test signals to be supplied to said electronic device.

3. A method as described in claim 2 , wherein said event associated with said first test domain comprises a programmed event in said test pattern.

4. A method as described in claim 2 , wherein said event associated with said first test domain comprises an event detected in outputs of said electronic device generated in response to said test signals supplied to said electronic device.

5. The method as described in claim 1 , further comprising:

(d) terminating said test initiated for said first test domain; and

(e) terminating said test initiated for said second test domain independently of said termination for said test for said first test domain.

6. The method as described in claim 5 , wherein said test initiated for said first test domain is terminated at a different time from said test initiated for said second test domain.

7. The method as described in claim 1 , wherein said test for said first test domain is carried out at a first clock speed and said test for said second test domain is carried out at a second clock speed that is different from said first clock speed.

8. The method as described in claim 1 , wherein a test pattern used in said test initiated for said first test domain is different from a test pattern used in said test initiated for said second domain.

9. The method as described in claim 1 , wherein said test and said triggers are defined as XML blocks and passed as objects.

10. A method as described in claim 1 , wherein said test for said first test domain is operable to interact with said second test domain via said trigger.

11. A method as described in claim 10 , wherein said trigger is generated during execution of said test for said first test domain.

12. A non-transitory computer-readable storage medium having computer-readable program code stored thereon for causing a computer system to execute a method for testing an electronic device using multiple test domains, said method comprising:

(a) initiating a test for a first test domain at a first instrument;

(b) generating a trigger at the first instrument in response to an event associated with the first test domain; and

(c) initiating a test for a second test domain at a second instrument in response to a receipt of the trigger at the second instrument,

wherein termination of said test for said first test domain is conditioned on an event in said second test domain.

13. The non-transitory computer readable storage medium as described in claim 12 , wherein said initiating said test for said first test domain further comprises executing a test pattern to generate test signals to be supplied to said electronic device.

14. A non-transitory computer-readable storage medium as described in claim 13 , wherein said event associated with said first test domain comprises a programmed event in said test pattern.

15. A non-transitory computer-readable storage medium as described in claim 13 , wherein said event associated with said first test domain comprises an event detected in outputs of said electronic device generated in response to said test signals supplied to said electronic device.

16. The non-transitory computer-readable storage medium as described in claim 12 , wherein said method further comprises:

(d) terminating said test initiated for said first test domain; and

(e) terminating said test initiated for said second test domain independently of said termination for said test for said first test domain.

17. The non-transitory computer-readable storage medium as described in claim 16 , wherein said test initiated for said first test domain is terminated at a different time from said test initiated for said second test domain.

18. The non-transitory computer-readable storage medium as described in claim 12 , wherein said test for said first test domain is carried out at a first clock speed and said test for said second test domain is carried out at a second clock speed that is different from said first clock speed.

19. The non-transitory computer-readable storage medium as described in claim 12 , wherein a test pattern used in said test initiated for said first test domain is different from a test pattern used in said test initiated for said second test domain.

20. The non-transitory computer readable storage medium as described in claim 12 , wherein said test and said triggers are defined as XML blocks and passed as objects.

21. A non-transitory computer-readable storage medium having stored therein program instructions to be executed in an apparatus for testing an electronic device, said method comprising:

(a) initiating a test for a first test region of said electronic device at a first test instrument of said apparatus;

(b) generating a trigger at said first test instrument in response to an event associated with said first test region of said electronic device; and

(c) initiating a test for a second test region of said electronic device at a second test instrument of said apparatus in response to a receipt of said trigger at the second test instrument,

wherein termination of said test for said first test region is conditioned on an event in said second test region.

22. The non-transitory computer-readable storage medium as described in claim 21 , wherein said program instructions define said test from said first test region separately for said test for said second test region, each such test definition specifying a test pattern and timing data to be used with said test.

23. The non-transitory computer-readable storage medium as described in claim 21 , wherein said initiating said test for said first test region further comprises executing a test pattern to generate test signals to be supplied to said first region of said electronic device.

24. The non-transitory computer-readable storage medium as described in claim 23 , wherein said event associated with said first test region comprises a programmed event in said test pattern.

25. The non-transitory computer-readable storage medium as described in claim 23 , wherein said event associated with said first test region comprises an event detected in outputs of said first test region of said electronic device generated in response to said test signals supplied to said first test region of said electronic device.

26. The non-transitory computer-readable storage medium as described in claim 21 , wherein said test for said first test region is carried out at a first clock speed and said test for said second test region is carried out at a second clock speed that is different from said first clock speed.

Assignments (8)
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS, RECORDED AT REEL 047185, FRAME 0624 Recorded Mar 7, 2024
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS AGENT
To: XCERRA CORPORATION
Reel/Frame 066762/0811 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT STATEMENT THAT THIS DOCUMENT SERVES AS AN OATH/DECLARATION PREVIOUSLY RECORDED ON REEL 047185 FRAME 0628. ASSIGNOR(S) HEREBY CONFIRMS THE PATENT SECURITY AGREEMENT. Recorded Nov 28, 2018
From: XCERRA CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 047675/0354 →
PATENT SECURITY AGREEMENT Recorded Oct 2, 2018
From: XCERRA CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 047185/0624 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 7261561 AND REPLACE WITH PATENT NUMBER 7231561 PREVIOUSLY RECORDED ON REEL 034660 FRAME 0188. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT. Recorded Feb 11, 2016
From: XCERRA CORPORATION; EVERETT CHARLES TECHNOLOGIES LLC
To: SILICON VALLEY BANK, AS ADMINISTRATIVE AGENT
Reel/Frame 037824/0372 →
SECURITY AGREEMENT Recorded Dec 18, 2014
From: XCERRA CORPORATION; EVERETT CHARLES TECHNOLOGIES LLC
To: SILICON VALLEY BANK, AS ADMINISTRATIVE AGENT
Reel/Frame 034660/0188 →
RELEASE OF SECURITY INTEREST IN UNITED STATES PATENTS Recorded Dec 18, 2014
From: SILICON VALLEY BANK, AS ADMINISTRATIVE AGENT
To: XCERRA CORPORATION; EVERETT CHARLES TECHNOLOGIES LLC
Reel/Frame 034660/0394 →
CHANGE OF NAME Recorded May 27, 2014
From: LTX-CREDENCE CORPORATION
To: XCERRA CORPORATION
Reel/Frame 033032/0768 →
SECURITY AGREEMENT Recorded Jan 17, 2014
From: LTX-CREDENCE CORPORATION; EVERETT CHARLES TECHNOLOGIES LLC
To: SILICON VALLEY BANK, AS ADMINISTRATIVE AGENT
Reel/Frame 032086/0476 →