Semiconductor memory device
View Patent ↗An apparatus for detecting a defect of a data transfer line in a semiconductor memory device, including a data transfer unit for transferring data between a local I/O line and a global I/O line; a data transfer controller for controlling the data transfer unit by generating a read signal, a write signal, and a local I/O line reset signal; a test mode controller for preventing an activation of the read signal, a column select signal and the local I/O line reset signal based on a test mode signal; a first temporary data storage for storing data of the global I/O line; and a second temporary data storage for storing data of the local I/O line.
1. An apparatus for detecting a defect of a data transfer line in a semiconductor memory device, comprising:
a data transfer unit for transferring data between a local I/O line and a global I/O line;
a data transfer controller for controlling the data transfer unit by generating a read signal, a write signal, and a local I/O line reset signal;
a test mode controller for preventing an activation of the read signal, a column select signal and the local I/O line reset signal based on a test mode signal;
a first temporary data storage for storing data of the global I/O line; and
a second temporary data storage for storing data of the local I/O line.
2. The apparatus of claim 1 , further comprising:
a test mode determiner for generating the test mode signal; and
a column decoder for outputting the column select signal to control a data transfer between a memory cell and the local I/O line.
3. The apparatus of claim 1 , wherein the test mode signal includes a first test mode signal for selecting the first temporary data storage and a second test mode signal for selecting the second temporary data storage.
4. The apparatus of claim 3 , wherein the test mode controller includes:
a first deactivating unit for preventing the activation of the read signal;
a second deactivating unit for preventing the activation of the column select signal; and
a third deactivating unit for preventing the activation of the local I/O line reset signal.
5. The apparatus of claim 4 , wherein the first deactivating unit includes:
a first inverter for inverting the first test mode signal;
a logic gate for performing a NAND operation of the read signal and an output signal of the first inverter; and
a second inverter for inverting an output signal of the logic gate.
6. The apparatus of claim 4 , wherein the second deactivating unit includes:
a logic gate for performing a NOR operation of the second test mode signal and the local I/O line reset signal; and
an inverter for inverting an output signal of the logic gate.
7. The apparatus of claim 1 , wherein the first temporary data storage and the second temporary data storage are optionally provided according to a defect detection area of the data transfer line.
8. The apparatus of claim 1 , wherein the first temporary data storage is implemented with an inverter latch circuit.
9. The apparatus of claim 1 , wherein the second temporary data storage includes the local I/O line.
10. A semiconductor memory device for detecting a defect of a data transfer line, comprising:
a data transfer unit for transferring data between a local I/O line and a global I/O line;
a data transfer controller for controlling the data transfer unit by generating a read signal and a write signal;
a test mode controller for preventing an activation of the read signal based on a test mode signal; and
a temporary data storage for storing data located in the global I/O line.
11. The semiconductor memory device of claim 10 , wherein the test mode controller includes:
a first inverter for inverting the test mode signal;
a logic gate for performing a NAND operation of the read signal and an output signal of the first inverter; and
a second inverter for inverting an output signal of the logic gate.
12. The semiconductor memory device of claim 10 , wherein the temporary data storage is implemented with an inverter latch circuit.
13. A semiconductor memory device for detecting a defect of a data transfer line, comprising:
a data transfer unit for transferring data between a local I/O line and a global I/O line;
a data transfer controller for controlling the data transfer unit by generating a local I/O line reset signal;
a test mode controller for preventing an activation of a column select signal and the local I/O line reset signal in response to a test mode signal;
a first temporary data storage for storing data located in the global I/O line; and
a second temporary data storage for storing data located in the local I/O line.
14. The semiconductor memory device of claim 13 , further comprising:
a test mode determiner for generating the test mode signal; and
a column decoder for outputting the column select signal to control a data transfer between a memory cell and the local I/O line.
15. The semiconductor memory device of claim 13 , wherein the test mode signal includes a first test mode signal for selecting the first temporary data storage and a second test mode signal for selecting the second temporary data storage.
16. The semiconductor memory device of claim 15 , wherein the test mode controller includes:
a first deactivating unit for preventing the activation of the column select signal; and
a second deactivating unit for preventing the activation of the local I/O line reset signal.
17. The semiconductor memory device of claim 16 , wherein the second deactivating unit includes:
a logic gate, inputs of the logic gate coupled to the second test mode signal and the local I/O line reset signal; and
an inverter for inverting an output signal of the logic gate.
18. The semiconductor memory device of claim 15 , wherein the first temporary data storage is implemented with an inverter latch circuit.
19. The semiconductor memory device of claim 15 , wherein the second temporary data storage includes the local I/O line.