Semiconductor memory device

1. A semiconductor memory device, comprising:

a bit line sense amplifier connected to a pair of bit lines;

a pair of first local lines connected to the pair of bit lines by a first switching unit;

a pair of second local lines connected to the pair of first local lines by a second switching unit; and

a writing driver for driving the second local lines with a normal-driving voltage in response to a data signal through a global line, wherein the writing driver drives the second local lines with an over-driving voltage having a higher level than the normal-driving voltage during a predetermined period.

2. The semiconductor memory device of claim 1 , wherein the normal-driving voltage is a voltage for operating the bit line sense amplifier.

3. The semiconductor memory device of claim 1 , wherein after the writing driver drives the second local lines with using the over-driving voltage, the writing driver drives the second local lines with the normal-driving voltage.

4. The semiconductor memory device of claim 1 , wherein the writing driver includes:

a first receiving unit for receiving the data signal, controlled by a reset signal for resetting the second local lines and an enable signal for enabling the writing driver;

a second receiving unit for receiving an inverted signal of the data signal, controlled by a reset signal for resetting the second local lines and an enable signal for enabling the writing driver;

a first driving unit for driving one of the second lines as a power supply voltage or a core voltage in response to outputs of the first and second receiving units and the enable signal; and

a second driving unit for driving the other of the second lines as a power supply voltage or a core voltage in response to outputs of the first and second receiving units and the enable signal.

5. The semiconductor memory device of claim 4 , wherein the first receiving unit includes:

a first PMOS transistor having a gate connected to the reset signal;

a first NMOS transistor having a gate connected to the enable signal;

a second NMOS transistor having a gate connected to the global line; and

a first latch for latching a signal supplied at a node between the first PMOS transistor and the first NMOS transistor.

6. The semiconductor memory device of claim 5 , wherein the second receiving unit includes:

a second PMOS transistor having a gate connected to the reset signal;

a third NMOS transistor having a gate connected to the enable signal;

a fourth NMOS transistor a gate for receiving an inverted signal of data signal of the global line; and

a second latch for latching a signal supplied at a node between the second PMOS transistor and the third NMOS transistor.

7. The semiconductor memory device of claim 6 , wherein the first driving unit includes:

a first normal driver for driving the one of the second lines as the core voltage;

a first over driver for driving the one of the second lines as the power supply voltage;

a first inverter for inverting the enable signal;

a first NAND gate for performing a NAND operation with an output of the first inverter and an output of the second receiving unit to output a control signal for operating the first normal driver; and

a second NAND gate for performing a NAND operation with the enable signal and an output of the second receiving unit to output a control signal for operating the first over driver.

8. The semiconductor memory device of claim 7 , wherein the second driving unit includes:

a second normal driver for driving the other of the second lines as the core voltage;

a second over driver for driving the other of the second lines as the power supply voltage;

a second inverter for inverting the enable signal;

a third NAND gate for performing a NAND operation with an output of the second inverter and an output of the first receiving unit to output a control signal for operating the second normal driver; and

a fourth NAND gate for performing a NAND operation with the enable signal and an output of the first receiving unit to output a control signal for operating the second over driver.

9. The semiconductor memory device of claim 1 , wherein the predetermined period is an initial predetermined period for driving the second local lines to transfer data signals to the local lines.

10. A method for operating a semiconductor memory device, comprising:

receiving a data signal through a global line in response to a write command;

driving a local line as an over-driving voltage in response to the data signal of the global line;

driving the local line as a normal-driving voltage in response to the data signal of the global line wherein the normal-driving voltage is lower than the over-driving voltage;

latching a data signal of the local line using a bit line sense amplifier; and

transferring the latched data into a unit cell.

11. The method of claim 10 , wherein the driving as an over driving voltage is only performed during an initial predetermined period for driving the local lines to transfer a data signal to the local line.

12. The method of claim 10 , wherein an operating voltage of the bit line sense amplifier is the normal-driving voltage.

13. A semiconductor memory device, comprising:

a pair of local lines;

a global line;

a writing driving unit for driving the local lines as a normal-driving voltage in response to a data signal input by a write command through the global line wherein the writing driving unit drives the local line as an over-driving voltage having a higher level than the normal-driving voltage during a predetermined period.

14. The semiconductor memory device of claim 13 , further comprising:

a pair of bit lines;

a bit line sense amplifier for latching data signals of the local lines and transferring the latched data signals into the bit lines; and

a connecting unit for connecting the bit line sense amplifier to the local lines.

15. The semiconductor memory device of claim 14 , wherein the predetermined period is an initial predetermined period for driving the local lines to transfer data signals to the local lines.

16. The semiconductor memory device of claim 15 , wherein the writing driving unit includes:

a first latch unit for latching a first logic level of the global line;

a second latch unit for latching a second logic level of the global line;

a first normal driver for driving the one local line of the local lines as the normal-driving voltage or a ground voltage in response to the latched signal by the first latch unit;

a second normal driver for driving the other local Line of the local lines as the normal-driving voltage or the ground voltage in response to the latched signal by the second latch unit;

a first over driver for driving the one local line as the over-driving voltage in response to the latched signals by the first and the second latch units; and

a second over driver for driving the other local line as the over-driving voltage in response to the latched signals by the first and the second latch units.

17. The semiconductor memory device of claim 15 , wherein the writing driving unit includes:

a latch unit for latching a data signal of the global line;

a normal driver for driving the local lines as the normal-driving voltage or a ground voltage in response to the latched signal by the latch unit; and

a over driver for driving the local lines as the over-driving voltage in response to the latched signal by the second latch units.