Semiconductor device

1. A semiconductor device, comprising:

a P-channel metal-oxide semiconductor (PMOS) transistor and an N-channel metal-oxide semiconductor (NMOS) transistor formed in three or more fin active regions in a vertical stack structure, each fin active region having a silicon-on-insulator (SOI) substrate including a first insulation layer, an N-type substrate, a second insulation layer, and a P-type substrate;

an input metal line contacting gates of the PMOS transistor and NMOS transistor;

a power supply voltage metal line contacting four channel active regions of the PMOS transistor;

a contact metal line contacting two channel active regions of the NMOS transistor; and

an output metal line contacting four channel active regions of the PMOS transistor and the NMOS transistor.

2. The semiconductor device of claim 1 , wherein each channel active region comprises a side portion surface of the fin active region.

3. The semiconductor device of claim 1 , wherein the PMOS transistor and the NMOS transistor comprise in cross-section:

the fin active regions having the SOI substrate including the first insulation layer, the N-type substrate, the second insulation layer, and the P-type substrate formed in sequential order;

gate insulation layers formed on both sides of the fin active regions;

a gate conductive layer covering four channel active regions of the fin active regions; and

a P-type source and a drain formed in the N-type substrate and an N-type source and a drain formed in the P-type substrate.

4. The semiconductor device of claim 1 , wherein the power supply voltage metal line comprises in cross-section:

the PMOS transistor and the NMOS transistor formed in the fin active regions in the vertical stack structure;

pad metal layers contacting sources formed in four side portion surfaces of the PMOS transistor;

sidewall insulation layers formed over sources formed in side portion surfaces of the NMOS transistor; and

the power supply voltage metal line contacting the pad metal layers.

5. The semiconductor device of claim 4 , wherein the sidewall insulation layers are formed using a low pressure chemical vapor deposition (LPCVD) method to obtain a thickness ranging from approximately 100 Å to approximately 200 Å.

6. The semiconductor device of claim 1 , wherein the contact metal line comprises in cross-section:

the PMOS transistor and the NMOS transistor formed in the fin active regions in the vertical stack structure; and

the contact metal line contacting sources formed in two side portion surfaces of the NMOS transistor.

7. The semiconductor device of claim 1 , wherein the output metal line comprises in cross-section:

the PMOS transistor and the NMOS transistor formed in the fin active regions in the vertical stack structure; and

the output metal line contacting drains formed in four side portion surfaces of the PMOS and NMOS transistors.

8. The semiconductor device of claim 1 , wherein the metal lines comprise a tungsten layer formed by employing a chemical vapor deposition (CVD) method.