Semiconductor device including semiconductor chip with two pad rows
View Patent ↗A semiconductor device includes a semiconductor chip having at a center area thereof first and second pad rows which include a plurality of first pads and a plurality of second pads, respectively. A package substrate is bonded to the semiconductor chip. The package substrate includes a substrate opening corresponding to a region including the first and second pad rows, first and second wiring positioned at opposite sides of the substrate opening, respectively, and a ball land disposed in the first wiring area. A bridge section is provided over the substrate opening to mutually connect the first and second wiring areas. The ball land is electrically connected to at least one of the second pads through the bridge section by a lead.
1. A semiconductor device comprising:
a semiconductor chip having at a center area thereof first and second pad rows which include a plurality of first pads and a plurality of second pads, respectively;
a package substrate bonded to the semiconductor chip, the package substrate including a substrate opening corresponding to a region including the first and second pad rows, first and second wiring areas positioned at opposite sides of the substrate opening, respectively, a plurality of first ball lands disposed in the first wiring area, a plurality of second ball lands disposed in the second wiring area, a plurality of first leads disposed in the first wiring area, and a plurality of second leads disposed in the second wiring area, each of the first leads being connected to an associated one of the first pads of the semiconductor chip, each of the second leads being connected to an associated one of the second pads of the semiconductor chip, the first ball lands including plural ball lands each connected to an associated one of the first leads, and the second ball lands including plural ball lands each connected to an associated one of the second leads;
a bridge section provided over the substrate opening; and
at least one third lead, the at least one third lead being connected at one end thereof to at least one of the first leads connected to the first pads of the semiconductor chip, passing over the bridge section, and being connected at the other end thereof to at least one of the second ball lands.
2. The semiconductor device according to claim 1 , further comprising an elastomer bonding the semiconductor chip and the package substrate to each other, the elastomer having an elastomer opening corresponding to a region including the first and second pad rows.
3. The semiconductor device according to claim 1 , wherein:
the package substrate includes a TAB tape; and
the substrate opening is formed in the TAB tape.
4. The semiconductor device according to claim 1 , wherein the bridge section is disposed at an end portion of the substrate opening such that the bridge section connects an end portion of the first wiring area and an end portion of the second wiring area neighboring the end portion of the first wiring area.
5. The semiconductor device according to claim 1 , further comprising:
a suspended pattern connected between a selected one of the first pads and a selected one of the second pads;
a selected one of the first leads extending from the first wiring area and connected to the selected one of the first pads; and
a selected one of the second leads extending from the second wiring area and connected to the selected one of the second pads.
6. The semiconductor device according to claim 5 , wherein:
connection of the selected one of the first leads and the suspended pattern to the selected one of the first pads is carried out by double-bonding; and
connection of the selected one of the second leads and the suspended pattern to the selected one of the second pads is carried out by double-bonding.
7. The semiconductor device according to claim 6 , wherein the suspended pattern has a GND (VSS) voltage or a power supply (VDD) voltage.
8. The semiconductor device according to claim 1 , further comprising an additional suspended pattern provided across the substrate opening and connected to the third lead.
9. The semiconductor device according to claim 8 , wherein the additional suspended pattern has a GND (VSS) voltage or a power supply (VDD) voltage.
10. The semiconductor device as claimed in claim 1 , wherein the at least one of the second ball lands has no electrical connection with any one of the second leads.
11. The semiconductor device as claimed in claim 1 , wherein the at least one of the second ball lands is included in the plural ball lands each connected with the associated one of the second leads.
12. The semiconductor device as claimed in claim 1 , wherein the bridge section includes a conductive layer thereon, the third lead including a first lead portion making an electrical path between the conductive later and one of the first pads of the semiconductor chip to which the at least one of the first leads is connected and a second lead portion making an electrical path between the conductive layer and one of the second pads of the semiconductor chip to which the at least one of the second ball lands is connected.
13. The semiconductor device as claimed in claim 3 , wherein the bridge section comprises a portion of the TAB tape.