Packet processor memory conflict prediction
View Patent ↗A mechanism receives memory reads and writes from a packet processing engine, each memory access having an associated packet identifier. Upon receiving a memory read, conflict prediction logic determines if a future conflict with a memory write is likely, and if so the processing of the memory read is delayed. After the write to which the read depends is received, the delayed memory read is allowed to complete. Such a delayed read mechanism can reduce or eliminate work discarded due to memory conflicts detected after the fact, while preserving the sequential semantics of the packet processor. The conflict prediction logic can be used in conjunction with conflict detection in which write data is buffered and information associated with both reads and writes is recorded.
1. An apparatus coupled to a packet processing engine and a memory subsystem comprising:
conflict prediction logic configured to receive memory reads from said packet processing engine and capable of asserting a delay read signal;
wherein when said packet processing engine generates a memory read having a first associated packet identifier, if said conflict prediction logic asserts said delay read signal, said memory read is delayed until said packet processing engine generates a first memory write having a second associated packet identifier.
2. The apparatus of claim 1 further comprising:
a data storage element storing data representing said memory read;
conflict detection logic for determining if a memory conflict exists between said memory read and a second memory write having a third associated packet identifier based on said first associated packet identifier and said third associated packet identifier; and
logic for signaling a conflict coupled to said conflict detection logic and utilizing said first associated packet identifier.
3. A method of predicting memory conflicts for a packet processing engine comprising the steps of:
receiving a memory read having a first associated packet identifier from said packet processing engine;
determining if said memory read is likely to depend on a future memory write, having a second associated packet identifier;
delaying said memory read until said future memory write is received based on said step of determining.
4. The method of claim 3 further comprising the steps of:
receiving a second memory write having a third associated packet identifier;
determining if a memory conflict exists between said memory read and said second memory write based on a comparison of said first associated packet identifier and said third associated packet identifier; and
signaling a conflict based on said step of determining, utilizing said first associated packet identifier.