Method of manufacturing interconnecting structure with vias
View Patent ↗First wirings and first dummy wirings are formed in a p-SiOC film formed on a substrate. A p-SiOC film is formed, and a cap film is formed on the p-SiOC film. A dual damascene wiring, including vias connected to the first wirings and the second wirings, is formed in the cap film and the p-SiOC film 22 . Dummy vias are formed on the periphery of isolated vias.
1. A method of manufacturing an interconnecting structure, the method comprising:
forming a first layer including a first metal wiring and an insulator;
forming an etching stopper layer containing nitrogen atoms on said first layer and in contact with said first metal wiring and said insulator;
forming an interlayer insulating layer on said etching stopper layer;
forming first and second via holes in said interlayer insulating layer, the first via hole reaching said etching stopper layer at a position directly opposite said first metal wiring and the second via hole reaching said etching stopper layer at a position directly opposite said insulator, the second via hole being located near the first via hole;
forming a resist pattern of a chemically amplified resist on said interlayer insulating layer and filling the second via hole with resist;
forming a groove for a second metal wiring only at an upper portion of the first via hole, remote from said first layer, by etching and removing only part of said interlayer insulating layer at the upper portion, using said resist pattern as an etching mask, the second via hole being located sufficiently near the first via hole so that, in forming the groove, resist poisoning is prevented; and
forming the second metal wiring in the groove, a first via in the first via hole as an isolated via, and a dummy via in the second via hole by embedding a metal in the groove and in the first and second via holes, respectively.
2. The method of manufacturing an interconnecting structure according to claim 1 , wherein said interlayer insulating layer includes a SiOC film.
3. The method of manufacturing an interconnecting structure according to claim 1 comprising, after forming said interlayer insulating layer, forming a cap layer on said interlayer insulating layer, and forming the first and second via holes to pass through said cap layer and into said interlayer insulating layer.
4. The method of manufacturing an interconnecting structure according to claim 1 including forming said first and second metal wirings and said first and second vias of metallic copper.
5. The method of manufacturing an interconnecting structure according to claim 1 , wherein forming the first and second via holes includes:
forming a photoresist pattern including first and second holes having respective shapes; and
etching said interlayer insulating layer, using the photoresist pattern as an etching mask, thereby forming the first via hole having a shape following the shape of the first hole and forming the second via hole having a shape following the shape of the second hole.
6. A method of manufacturing an interconnecting structure, the method comprising:
forming a first layer including a first metal wiring and an insulator;
forming an etching stopper layer containing nitrogen atoms on said first layer and in contact with said first metal wiring and said insulator;
forming an interlayer insulating layer on said etching stopper layer;
forming first and second via holes in said interlayer insulating layer, the first via hole reaching said etching stopper layer at a position directly opposite said first metal wiring, and the second via hole reaching said etching stopper layer at a position directly opposite said insulator, and the second via hole being located near the first via hole;
forming a resist pattern of a chemically amplified resist on said interlayer insulating layer and filling the second via hole with resist;
forming a groove for a second metal wiring only at an upper portion of the first via hole, remote from said first layer, by etching and removing only part of said interlayer insulating layer at the upper portion, using said resist pattern as an etching mask, the groove having a width larger than openings of the first and second via holes in said interlayer insulating layer, the second via hole being located sufficiently near the first via hole so that, in forming the groove, resist poisoning is prevented; and
forming the second metal wiring and a via by embedding a metal in the groove and in the first via hole.