Cavity chip package

1. A chip package for attaching a semiconductor die having an active surface, the active surface having a bump region with die conductive bumps thereon and a peripheral region without die conductive bumps, the chip package comprising:

a carrier substrate having first and second major surfaces;

a cavity formed on the first major surface of the carrier substrate, the cavity having a height H 1 and a cavity bottom surface with contacts pads disposed thereon, wherein the height H 1 is selected such that when the semiconductor die is attached, the die conductive bumps are coupled to the contact pads in the cavity and at least portions of the peripheral region of the active surface are mounted to a top surface of the cavity; and

package contacts disposed on one of the first or second major surfaces, wherein the contact pads are electrically coupled to the package contacts.

2. The chip package of claim 1 further comprises underfill material in the cavity, the underfill material at least fills the space between the semiconductor die and the cavity bottom surface.

3. The chip package of claim 1 wherein the package comprises a semiconductor die attached to the carrier, the semiconductor die comprises a flip chip.

4. The chip package of claim 3 further comprises underfill material in the cavity, the underfill material at least fills the space between the semiconductor die and the cavity bottom surface.

5. The chip package of claim 1 wherein the cavity comprises first and second sub-cavities, the first sub-cavity comprises the cavity bottom surface with the height H 1 and the second sub-cavity is larger than the first sub-cavity, wherein when the semiconductor die is attached, the die conductive bumps are coupled to the contact pads and at least portions of the peripheral region of the active surface are mounted on a top surface of the first sub-cavity.

6. The chip package of claim 5 wherein the carrier substrate comprises base and supplemental layers, the base layer serves as the cavity bottom surface of the first sub-cavity and the supplemental layers form sidewalls of the first and second sub-cavities.

7. The chip package of claim 5 wherein the second sub-cavity comprises a second sub-cavity height H 2 ,wherein H 2 is at least equal to or greater than a thickness of the semiconductor die.

8. The chip package of claim 7 wherein the carrier substrate comprises base and supplemental layers, the base layer serves as the cavity bottom surface of the first sub-cavity and the supplemental layers form sidewalls of the first and second sub-cavities.

9. The chip package of claim 1 wherein

the cavity comprises a plurality of sub-cavities, wherein n and n- 1 sub-cavities of the plurality of sub-cavities are arranged such that the n sub-cavity is above and larger than the n- 1 sub-cavity, the n- 1 sub-cavity comprises the height H 1 and contact pads at n- 1 cavity bottom surface, wherein when the semiconductor die is attached, the die conductive bumps are coupled to the contact pads in the n- 1 cavity bottom surface and at least portions of the peripheral region of the active surface are mounted on n- 1 cavity top surface.

10. The chip package of claim 9 wherein the carrier substrate comprises base and supplemental layers, the base layer serves as the cavity bottom surface of the first of the plurality of sub-cavities and the supplemental layers form sidewalls of other of the plurality of sub-cavities.

11. The chip package of claim 9 wherein the n sub-cavity comprises a n sub-cavity height H n , wherein H n is at least equal to or greater than a thickness of the semiconductor die.

12. The chip package of claim 11 wherein the carrier substrate comprises base and supplemental layers, the base layer serves as the cavity bottom surface of the first of the plurality of sub-cavities and the supplemental layers form sidewalls of the other of the plurality of sub-cavities.

13. A chip package for attaching a semiconductor die having an active surface, the active surface having a bump region with die conductive bumps thereon and a peripheral region without die conductive bumps, the chip package comprising:

a carrier substrate having first and second major surfaces;

a cavity formed on the first major surface of the carrier substrate, the cavity comprising a plurality of sub-cavities formed by a plurality of at least partially concentric openings, wherein n and n- 1 sub-cavities of the plurality of sub-cavities are arranged such that the n sub-cavity is above and larger than the n- 1 sub-cavity, the n- 1 sub-cavity comprises the height H 1 and contact pads at n- 1 cavity bottom surface, wherein when the semiconductor die is attached, the die conductive bumps are coupled to the contact pads and at least portions of the peripheral region of the active surface are mounted on at least portions of a top surface of n- 1 sub-cavity; and

package contacts disposed on one of the major surfaces, wherein the contact pads are electrically coupled to the package contacts.

14. The chip package of claim 13 wherein the n sub-cavity comprises a n sub-cavity height H n , wherein H n is at least greater than a thickness of the semiconductor die.

15. The chip package of claim 13 wherein the carrier substrate comprises base and supplemental layers, the base layer serves as the cavity bottom surface of the first of the plurality of sub-cavities and the supplemental layers form sidewalls of the other of the plurality of sub-cavities.

16. A method of chip packaging comprising:

providing a carrier having a cavity formed on a first major surface thereof the cavity including a cavity bottom surface having package pads and a height H 1 ;

providing a semiconductor die with an active surface having a bump region with die conductive bumps thereon and a peripheral region without die conductive bumps; and

attaching a semiconductor die to the carrier, wherein the height H 1 is selected such that conductive bumps are mated to contact pads and at least portions of the peripheral region of the active surface are securely attached to at a top surface of the cavity by an adhesive material.

17. The method of claim 16 further comprises providing an underfill material in the cavity, the underfill material at least fills the space between the semiconductor die and the cavity bottom surface.

18. The method of claim 16 wherein providing a semiconductor die comprises providing a flip chip.

19. The method of claim 18 further comprises providing an underfill material in the cavity, the underfill material at least fills the space between the semiconductor die and the cavity bottom surface.

20. The method of claim 16 wherein:

the cavity comprises first and second sub-cavities, the first sub-cavity comprises the cavity bottom surface with the height H 1 and the second sub-cavity is larger than the first sub-cavity; and

H 1 is selected such that the die conductive bumps are mated to the contact pads and at least portions of the peripheral region of the active surface are securely attached to a top surface of the first sub-cavity.

21. The method of 20 wherein the second sub-cavity comprises a second sub-cavity height H 2 , wherein H 2 is at least equal to or greater than a thickness of the semiconductor die.

22. The method of claim 16 wherein:

the cavity comprises a plurality of sub-cavities, wherein n and n- 1 sub-cavities of the plurality of sub-cavities are arranged such that the n sub-cavity is above and larger than the n- 1 sub-cavity, the n- 1 sub-cavity comprises the height H 1 and contact pads at n- 1 cavity bottom surface; and

H 1 is selected such that the die conductive bumps are mated to the contact pads and at least portions of the peripheral region of the active surface are securely attached to a top surface of the n- 1 sub-cavity.

23. The method of 22 wherein then sub-cavity comprises an sub-cavity height H n , wherein H n is at least equal to or greater than a thickness of the semiconductor die.