Comparator feedback peak detector
View Patent ↗There is disclosed a circuit and a process for detecting peak-to-peak voltage. The circuit comprises a first comparator having an output coupled to a first capacitor, a non-inverting input for receiving a high frequency AC waveform, and an inverting input, a second comparator having an output coupled to a second capacitor, and a first second input, an operational amplifier having a non-inverting input coupled to the inverting input of the first comparator, and an inverting input coupled to the first input. The process comprises charging a first capacitor when a high frequency AC waveform voltage is greater than a buffered voltage of the first capacitor, charging a second capacitor when an inverted buffered voltage of the second capacitor is greater than the high frequency AC waveform voltage, and outputting a voltage based on the buffered voltage of the first capacitor and the inverted buffered voltage of the second capacitor.
1. A process of detecting peak-to-peak voltage comprising:
performing a first comparison of a high frequency AC waveform voltage to a buffered voltage of a first capacitor;
charging the first capacitor responsive to the first comparison indicating the high frequency AC waveform voltage is greater than the buffered voltage of the first capacitor;
inverting a buffered voltage of a second capacitor;
performing a second comparison of the inverted buffered voltage of the second capacitor to the high frequency AC waveform voltage;
charging the second capacitor responsive to the second comparison indicating the inverted buffered voltage of the second capacitor is greater than the high frequency AC waveform voltage; and
outputting a voltage based on a difference between the buffered voltage of the first capacitor and the inverted buffered voltage of the second capacitor, the output voltage indicative of a peak-to-peak voltage of the high frequency AC waveform voltage.
2. The process of detecting peak-to-peak voltage of claim 1 , further comprising:
preventing the capacitors from discharging while outputting the voltage.
3. The process of detecting peak-to-peak voltage of claim 2 , further comprising:
closing a first and second FET switch to cause the capacitors to respectively discharge.
4. The process of detecting peak-to-peak voltage of claim 2 , further comprising:
digitizing the voltage, storing the digitized voltage and a time datum in a capture memory, wherein the FET switches are opened periodically at a fixed interval.
5. The process of detecting peak-to-peak voltage of claim 4 further comprising:
calculating an average waveform envelope based on the digital voltage and the time datum in the capture memory.
6. A process of detecting peak-to-peak voltage comprising:
performing a first comparison of a high frequency AC waveform voltage to a buffered voltage of a first capacitor;
charging the first capacitor responsive to the first comparison indicating the-high frequency AC waveform voltage is greater than the buffered voltage of the first capacitor;
inverting the high frequency AC waveform voltage;
performing a second comparison of the inverted high frequency AC waveform voltage to a buffered voltage of a second capacitor;
charging the second capacitor responsive to the second comparison indicating the inverted AC waveform voltage is greater than the buffered voltage of the second capacitor; and
outputting a voltage based on a sum of the buffered voltages of the capacitors, the output voltage indicative of a peak-to-peak voltage of the high frequency AC waveform voltage.
7. The process of detecting peak-to-peak voltage of claim 6 , further comprising:
preventing the capacitors from discharging while outputting the voltage.
8. The process of detecting peak-to-peak voltage of claim 7 , further comprising:
closing a first and second FET switch to cause the capacitors to respectively discharge.
9. The process of detecting peak-to-peak voltage of claim 8 , further comprising:
digitizing the voltage, storing the digitized voltage and a time datum in a capture memory, wherein the FET switches are opened periodically at a fixed interval.
10. The process of detecting peak-to-peak voltage of claim 9 , further comprising:
calculating an average waveform envelope based on the digital voltage and the time datum in the capture memory.
11. The process of detecting peak-to-peak voltage of claim 6 , further comprising:
producing the sum of the buffered voltages of the capacitors.