Method for forming a gate within a trench including the use of a protective film
View Patent ↗Gate trenches 108 are formed in a memory cell region M using a silicon nitride film 103 as a mask in a state in which the semiconductor substrate 100 in a P-type peripheral circuit region P and an N-type peripheral circuit region N is covered by a gate insulating film 101 s , a protective film 102 , and the silicon nitride film 103 . A gate insulating film 109 is then formed on the inner walls of the gate trenches 108 , and a silicon film 110 that includes an N-type impurity is embedded in the gate trenches 108 . The silicon nitride film 103 is then removed, and a non-doped silicon film is formed on the entire surface, after which a P-type impurity is introduced into the non-doped silicon film on region P, and an N-type impurity is introduced into the non-doped silicon film on regions M and N.
1. A method of manufacturing a semiconductor device, comprising:
covering second and third portions of a semiconductor layer with first and second stack structures, respectively, the first stack structure including a first gate insulating film and a first gate electrode material layer on the first gate insulating film, and the second stack structure including a second gate insulating film and a second gate electrode material layer on the second gate insulating film;
selectively forming a trench in a first portion of the semiconductor layer after said covering the second and third portions;
forming a third gate electrode material layer in the trench with an intervention of a third gate insulating film therebetween while covering the second and third portions of the semiconductor layer respectively with first and second stack structures;
forming a fourth gate electrode material layer in contact respectively with the first, second and third gate electrode materials; and
selectively removing the first, second and fourth gate electrode material layers to form first, second and third gate electrodes respectively on the first, second and third portions of the semiconductor layer, the first gate electrode comprising the third gate electrode material layer and a first part of the fourth gate electrode material layer, the second gate electrode comprising a part of the first gate electrode material layer and a second part of the fourth gate electrode material layer, and the third gate electrode comprising a part of the second gate electrode material layer and a third part of the fourth gate electrode material layer.
2. The method as claimed in claim 1 , wherein each of the first, second, third and fourth gate electrode material layers comprises a silicon layer.
3. The method as claimed in claim 1 , wherein the third gate electrode material layer is doped with an impurity before the forming a fourth gate electrode material layer, and the first and second gate electrode material layers and the first, second and third parts of the fourth gate electrode material layers are doped with respective impurities before the selectively removing.
4. The method as claimed in claim 3 , wherein each of the impurities doped respectively in the third gate electrode material layer, the first gate electrode material layer and the first and second parts of the fourth gate electrode material layer represents one conductivity type and each of the impurities doped in the second gate electrode material layer and the third part of the fourth gate electrode material layer represent the other conductive type.
5. The method as claimed in claim 1 , wherein the third gate electrode material layer is doped with an impurity indicative of one conductivity type before the forming a fourth gate electrode material layer, and wherein the first and second parts of the fourth gate electrode material layer and the first gate electrode material layer being doped with an impurity indicative of the one conductivity type simultaneously with one another and the third part of the fourth gate electrode material layer and the second gate electrode material layer are doped with an impurity indicative of the other conductivity type simultaneously with each other.
6. The method as claimed in claim 5 , wherein the one conductivity type is N type and the other conductive type is P type.
7. The method as claimed in claim 1 , wherein the first stack structure further includes a first insulating layer on the first gate electrode material layer, and the second stack structure further includes a second insulating layer on the second gate electrode material layer, the method further comprising removing the first and second insulating layers after the forming a third gate electrode material layer and before the forming a fourth gate electrode material layer.