Bond pad structures and integrated circuit chip having the same
View Patent ↗Bonding pad structures and integrated circuits having the same are provided. An exemplary embodiment of a bond pad structure comprises a bond pad layer. A passivation layer partially covers the bond pad layer from edges thereof and exposes a bonding surface, wherein the passivation layer is formed with a recess on at least one edge of the bonding surface to thereby define a probe needle contact area for probe needle testing and a wire bonding area for wire bonding on the bonding surface, and the probe needle contact area and the wire bonding area have a non-overlapping relationship.
1. A bond pad structure comprising:
a dielectric layer exposed with a bond pad layer; and
a passivation layer partially overlying the dielectric layer, covering the bond pad layer from edges thereof and exposing a bonding surface therein, wherein the passivation layer is formed with at least one opening enclosed by sides thereof neighboring one side of the bond pad layer, defining a probe needle contact area for probe needle testing and a wire bonding area for wire bonding on the bonding surface, the probe needle contact area and the wire bonding area have a non-overlapping relationship, wherein the at least one opening exposes an underlying passivation layer between the passivation layer and the dielectric layer, the at least one opening has an bottom surface, and the entire bottom surface of the opening is the underlying passivation layer.
2. The bonding pad structure of claim 1 , wherein the opening is in a distance D of about 0-5 μm from an edge of the bond pad layer.
3. The bonding pad structure of claim 1 , wherein the bond pad layer comprises aluminum, copper, or alloys thereof.
4. The bonding pad structure of claim 1 , wherein the opening has rectangular configuration and is enclosed by four sides.
5. The bonding pad structure of claim 1 , wherein the at least one opening comprises two openings neighboring opposite sides of the bond pad layer.
6. An integrated circuit chip, comprising:
a dielectric layer exposed with a plurality of bond pads thereon; and
a plurality of patterned passivation layers overlying portions of the dielectric layer, each partially covering one of the bond pad layers from edges thereof and respectively exposing a bonding surface therein, wherein at least one of the patterned passivation layers is formed with at least one opening enclosed by sides thereof neighboring one side of one of the bond pad layers, defining a probe needle contact area for probe needle testing and a wire bonding area for wire bonding on the bonding surface, the probe needle contact area and the wire bonding area have a non-overlapping relationship, and the patterned passivation layers covering two adjacent bond pads are isolated form each other by a gap over the dielectric layer defined therebetween, wherein the at least one opening exposes an underlying passivation layer between the passivation layer and the dielectric layer, the at least one opening has an bottom surface, and the entire bottom surface of the opening is the underlying passivation layer.
7. The integrated circuit chip of claim 6 , wherein the opening is in a distance D of about 0-5 μm from an edge of the bond pad layer.
8. The integrated circuit chip of claim 6 , wherein the bond pads comprise aluminum, copper, or alloys thereof.
9. The integrated circuit chip of claim 6 , wherein the opening has rectangular configuration and is enclosed by four sides.
10. The integrated circuit chip of claim 6 , wherein the at least one opening comprises two openings neighboring opposite sides of the bond pad layer.