Using thin undoped TEOS with BPTEOS ILD or BPTEOS ILD alone to improve charge loss and contact resistance in multi-bit memory devices
The present invention facilitates dual bit memory devices and operation of dual bit memory device by providing systems and methods that employ a relatively thin undoped TEOS liner during fabrication, instead of a relatively thick TEOS layer that is conventionally used. Employment of the relatively thin liner facilitates dual bit memory device operation by mitigating charge loss and contact resistance while providing protection against unwanted dopant diffusion. The present invention includes utilizing a relatively thin undoped TEOS liner that is formed on wordlines and portions of a charge trapping dielectric layer. The relatively thin undoped TEOS liner is formed with a thickness of less than about 400 Angstroms so that contact resistance and charge loss are improved and yet providing suitable protection for operation of the device. Additionally, the present invention includes foregoing with an undoped TEOS liner altogether.
1 . A dual bit memory device comprising:
a charge trapping dielectric layer formed on a semiconductor substrate;
bitlines formed in the semiconductor substrate that respectively operation as an acting source and acting drain;
wordlines formed on the charge trapping dielectric layer orthogonal to the bitlines;
a relatively thin undoped TEOS liner formed on the wordlines and portions of the charge trapping dielectric layer; and
an interlayer dielectric layer doped with boron and phosphor formed on the relatively thin undoped TEOS liner.
2 . The dual bit memory device of claim 1 , further comprising:
bitline contacts formed in the interlayer dielectric layer and through a portion of the relatively thin undoped TEOS liner and in contact with associated bitlines, defining interfaces between the bitline contacts and the associated bitlines that have a relatively low contact resistance.
3 . The dual bit memory device of claim 1 , further comprising:
wordline contacts formed in the interlayer dielectric layer and through a portion of the relatively thin undoped TEOS liner and in contact with associated wordlines, defining interfaces between the wordline contacts and the associated wordlines that have a relatively low contact resistance.
4 . The dual bit memory device of claim 3 , wherein the interface includes a salicide region that further reduces contact resistance.
5 . The dual bit memory device of claim 1 , wherein the relatively thin undoped TEOS liner has a thickness of less than 400 Angstroms.
6 . The dual bit memory device of claim 1 , wherein the relatively thin undoped TEOS liner has a thickness of less than 100 Angstroms.