CMOS device with zero soft error rate
A CMOS device and method of manufacture is provided for producing an integrated circuit that is not susceptible to various soft errors such as single-event upsets, multi-bit upsets or single-event latchup. The CMOS device and method utilizes a new and novel well architecture in conjunction with metal source/drain electrodes to eliminate soft errors. In one embodiment, the CMOS device uses a first metal source/drain material for the NMOS device and a second metal source/drain material for the PMOS device. The CMOS device further uses a multi-layered well-structure with a shallow N-well and a buried P-well for the PMOS device and a shallow P-well and a buried N-well for the NMOS device.
1. A CMOS device comprising:
a P-type semiconductor substrate, the P-type semiconductor substrate having a top surface and a bottom surface;
a first isolation region, the first isolation region extending a first distance into the P-type semiconductor substrate from the top surface of the P-type semiconductor substrate;
an NMOS active region including:
a buried N-well located on the P-type semiconductor substrate;
a P-well located on the buried N-well; and
at least one Schottky barrier NMOS device located on the P-well;
a PMOS active region including:
an N-well located on the P-type semiconductor substrate; and
at least one Schottky barrier PMOS device located on the N-well;
wherein the buried N-well of the NMOS active region is not electrically contacted via ohmic contacts;
wherein the buried N-well of the NMOS active region forms a metallurgical junction with the P-type semiconductor substrate, the metallurgical junction located a second distance into the P-type semiconductor substrate from the surface of the P-type substrate, wherein the second distance is less than the first distance; and
wherein the NMOS active region and the PMOS active region are electrically insulated from one another by the first isolation region.
2. The device of claim 1 , wherein the P-well forms a metallurgical junction with the buried N-well, wherein the metallurgical junction between the P-well and the N-well is located about 50 nm to about 1000 nm distant from a source and a drain of the at least one Schottky barrier NMOS device.
3. The device of claim 1 , wherein the N-well forms a metallurgical junction with the P-type semiconductor substrate, wherein the metallurgical junction between the N-well and the P-type semiconductor is located about 50 nm to about 1000 nm distant from a source and a drain of the at least one Schottky barrier NMOS device.
4. The device of claim 1 , wherein the at least one Schottky barrier NMOS further includes:
a gate located on a major surface of the P-well, the major surface located opposite a junction formed between the P-well and the buried N-well; and
a source electrode and a drain electrode configured to electrically contact an N-channel region and the P-well, wherein the N-channel region is formed at an interface between the gate and the P-well when an appropriate voltage is applied to the gate and further wherein the source electrode and the drain electrode each form a Schottky barrier with the N-channel region and the P-well.
5. The device of claim 4 , wherein the gate includes:
a gate insulator located on the top surface of the P-well;
a gate electrode located on the gate insulator, the gate electrode having a horizontal surface that is parallel to the top surface of the P-well and a vertical surface that is perpendicular to the top surface of the P-well; and
a gate sidewall insulator located on the vertical surface of the gate electrode.
6. The device of claim 5 , wherein the gate insulator includes a high k dielectric material.
7. The device of claim 4 , wherein the source electrode and the drain electrode each include a metal silicide.
8. The device of claim 7 , wherein the metal silicide includes a member of the group consisting of: Platinum Silicide, Palladium Silicide, and Iridium Silicide.
9. The device of claim 4 , wherein the N-channel region is strained.
10. The device of claim 1 , wherein the at least one Schottky barrier PMOS further includes:
a gate located on a major surface of the N-well, the major surface located opposite a junction formed between the N-well and the P-type semiconductor substrate; and
a source electrode and a drain electrode configured to electrically contact a P-channel region and the N-well, wherein the P-channel region is formed at an interface between the gate and the N-well when an appropriate voltage is applied to the gate and further wherein the source electrode and the drain electrode each form a Schottky barrier with the P-channel region and the N-well.
11. The device of claim 10 , wherein the gate includes:
a gate insulator located on the top surface of the N-well;
a gate electrode located on the gate insulator, the gate electrode having a horizontal surface that is parallel to the top surface of the N-well and a vertical surface that is perpendicular to the top surface of the N-well; and
a gate sidewall insulator located on the vertical surface of the gate electrode.
12. The device of claim 11 , wherein the gate insulator includes a high k dielectric material.
13. The device of claim 10 , wherein the source electrode and the drain electrode each include a metal silicide.
14. The device of claim 13 , wherein the metal silicide includes a rare-earth silicide.
15. The device of claim 10 , wherein the P-channel region is strained.
16. The device of claim 1 , wherein the P-well of the at least one Schottky barrier NMOS device is not electrically contacted via ohmic contacts.
17. The device of claim 1 , wherein the N-well of the at least one Schottky barrier PMOS device is not electrically contacted via ohmic contacts.
18. A CMOS device comprising:
an N-type semiconductor substrate, the N-type semiconductor substrate having a top surface and a bottom surface;
a first isolation region, the first isolation region extending a first distance into the N-type semiconductor substrate from the top surface of the N-type semiconductor substrate;
an NMOS active region including:
a P-well located on the N-type semiconductor substrate; and
at least one Schottky barrier NMOS device located on the P-well;
a PMOS active region including:
a buried P-well located on the N-type semiconductor substrate;
an N-well located on the buried P-well; and
at least one Schottky barrier PMOS device located on the N-well;
wherein the buried P-well of the PMOS active region is not electrically contacted via ohmic contacts;
wherein the buried P-well of the PMOS active region forms a metallurgical junction with the N-type semiconductor substrate, the metallurgical junction located a second distance into the N-type semiconductor substrate from the surface of the N-type substrate, wherein the second distance is less than the first distance; and
wherein the NMOS active region and the PMOS active region are electrically insulated from one another by the first isolation region.
19. The device of claim 18 , wherein the N-well forms a metallurgical junction with the buried P-well, wherein the metallurgical junction between the N-well and the P-well is located about 50 nm to about 1000 nm distant from a source and a drain of the at least one Schottky barrier PMOS device.
20. A CMOS device comprising:
a P-type semiconductor substrate, the P-type semiconductor substrate having a top surface and a bottom surface;
an NMOS active region including:
a buried N-well located on the P-type semiconductor substrate;
a P-well located on the buried N-well; and
at least one Schottky barrier NMOS device located on the P-well;
a PMOS active region including:
an N-well located on the P-type semiconductor substrate; and
at least one Schottky barrier PMOS device located on the N-well;
a first isolation region, wherein the first isolation region is located between the NMOS active region and the PMOS active region, wherein the first isolation region extends a first distance into the P-type semiconductor substrate from the top surface of the P-type semiconductor substrate, wherein the buried N-well of the NMOS active region forms a metallurgical junction with the P-type semiconductor substrate, wherein the metallurgical junction is located a second distance into the P-type semiconductor substrate from the surface of the P-type substrate, and wherein the second distance is less than the first distance.