IP Library Granted Patent US 7,682,912
Granted Patent B2
US 7,682,912 · App. 11/554,859 · Granted Mar 23, 2010

III-V compound semiconductor device with a surface layer in access regions having charge of polarity opposite to channel charge and method of making the same

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,682,912
App. No.
11/554,859
Granted
Mar 23, 2010
Kind
B2
Abstract

A method of forming a III-V compound semiconductor structure ( 10 ) comprises providing a III-V compound semiconductor substrate including a semi-insulating substrate ( 12 ) having at least one epitaxial layer formed thereon and further having a gate insulator ( 14 ) overlying the at least one epitaxial layer. The at least one epitaxial layer formed on the semi-insulating substrate comprises an epi-structure suitable for use in the formation of a channel of a III-V compound semiconductor MOSFET device, wherein the channel ( 30 ) having a first polarity. The method further comprises forming a charge layer ( 22 ) at a surface of the gate insulator, the charge layer having a second polarity, wherein the second polarity is opposite to the first polarity.

Claims (34)

1. A method of forming a III-V compound semiconductor structure, comprising:

providing a III-V compound semiconductor substrate including a semi-insulating substrate having at least one epitaxial layer formed thereon, and further having a gate insulator overlying the at least one epitaxial layer, wherein the at least one epitaxial layer formed on the semi-insulating substrate comprises an epi-structure suitable for use in the formation of a channel of a III-V compound semiconductor MOSFET device, the channel having a first polarity;

forming a charge layer at a surface of the gate insulator, the charge layer having a second polarity, wherein the second polarity is opposite to the first polarity;

forming source and drain contacts, wherein the source and drain contacts extend from the surface of the compound semiconductor structure and into the epi-structure, wherein forming the source and drain contacts defines a channel region within the epi-structure between the source and drain contacts; and

forming a gate contact overlying the gate insulator and positioned between a location of the source and drain contacts, wherein forming the gate contact includes forming the gate contact in a gate region, further in the absence of the charge layer at the surface of the gate insulator underlying the gate contact in the gate region, wherein a portion of the charge layer at the surface of the gate insulator remains in access regions defined by a first access region extending between the source contact and the gate contact and a second access region extending between the drain contact and the gate contact.

2. The method of claim 1 , wherein forming the gate contact includes removing the charge layer at the surface of the gate insulator in the location of the gate contact during formation of the gate contact.

3. The method of claim 1 , wherein forming the gate contact includes forming the gate contact prior to forming the charge layer at the surface of the gate insulator.

4. The method of claim 1 , wherein the gate region includes the gate contact overlying the gate insulator in the absence of the charge layer at the surface underlying the gate contact, the gate region further extending from the gate contact and into a portion of the channel underlying the gate contact,

wherein the first access region further extends from the charge layer at the surface of the gate insulator in the first access region and into a portion of the channel underlying the first access region between the source contact and the gate contact, and

wherein the second access region further extends between the drain contact and the gate contact at the surface of the gate insulator in the second access region and into a portion of the channel underlying the second access region between the drain contact and the gate contact.

5. The method of claim 1 , wherein the charge layer is configured to render an electron density in the portion of the channel of the first and second access regions to be greater than an electron density in the portion of the channel in the gate region.

6. The method of claim 1 , wherein the charge layer in the access regions decouples a charge density in the portion of the channel in the access regions from a charge density in the portion of the channel in the gate region.

7. The method of claim 6 , wherein a channel drive current capability of the III-V compound semiconductor MOSFET device is increased over a channel drive current capability of a similar, but absent the charge layer, III-V compound semiconductor MOSFET device.

8. The method of claim 1 , further wherein the charge layer in the access regions decouples a channel drive current of the III-V compound semiconductor MOSFET device from a threshold voltage of the III-V compound semiconductor MOSFET device.

9. The method of claim 1 , further comprising:

forming a cap layer overlying the charge layer, wherein the charge layer is formed during the initial stage of depositing the cap layer and the cap layer preserves the polarity of the charge layer during subsequent processing.

10. The method of claim 9 , wherein the cap layer comprises aluminum nitride (AIN).

11. The method of claim 1 , wherein the gate contact comprises a gate metal contact, and wherein the source and drain contacts comprise metal contacts.

12. The method of claim 1 , wherein the gate insulator comprises a gate oxide.

13. The method of claim 1 , wherein the III-V compound semiconductor substrate comprises an InP substrate.

14. The method of claim 1 , wherein the first polarity is negative and the second polarity is positive.

15. A III-V compound semiconductor MOSFET device having a III-V compound semiconductor substrate with a charge layer formed by the method of claim 1 .

16. A method of forming a III-V compound semiconductor structure, comprising:

providing a III-V compound semiconductor substrate including a semi-insulating substrate having at least one epitaxial layer formed thereon, and further having a gate insulator overlying the at least one epitaxial layer, wherein the at least one epitaxial layer formed on the semi-insulating substrate comprises an epi-structure suitable for use in the formation of a channel of a III-V compound semiconductor MOSFET device, the channel having a first polarity;

forming a charge layer at a surface of the gate insulator, the charge layer having a second polarity, wherein the second polarity is opposite to the first polarity;

forming source and drain contacts, wherein the source and drain contacts extend from the surface of the compound semiconductor structure and into the epi-structure, wherein forming the source and drain contacts defines a channel region within the epi-structure between the source and drain contacts; and

forming a gate contact overlying the gate insulator and positioned between a location of the source and drain contacts, wherein forming the gate contact includes forming the gate contact in a gate region, further in the absence of the charge layer at the surface of the gate insulator underlying the gate contact in the gate region, wherein a portion of the charge layer at the surface of the gate insulator remains in access regions defined by a first access region extending between the source contact and the gate contact and a second access region extending between the drain contact and the gate contact,

wherein the gate region includes the gate contact overlying the gate insulator in the absence of the charge layer at the surface underlying the gate contact, the gate region further extending from the gate contact and into a portion of the channel underlying the gate contact,

wherein the first access region further extends from the charge layer at the surface of the gate insulator in the first access region and into a portion of the channel underlying the first access region between the source contact and the gate contact,

wherein the second access region further extends between the drain contact and the gate contact at the surface of the gate insulator in the second access region and into a portion of the channel underlying the second access region between the drain contact and the gate contact, and

wherein the charge layer in the access regions decouples a charge density in the portion of the channel in the access regions from a charge density in the portion of the channel in the gate region.

17. The method of claim 16 , wherein forming the gate contact includes removing the charge layer at the surface of the gate insulator in the location of the gate contact during formation of the gate contact.

18. The method of claim 16 , wherein forming the gate contact includes forming the gate contact prior to forming the charge layer at the surface of the gate insulator.

19. A III-V compound semiconductor MOSFET device having a III-V compound semiconductor substrate with a charge layer formed by the method of claim 16 .

Assignments (30)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040632 FRAME: 0001. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Sep 21, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 044209/0047 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040632/0001 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0120 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0194 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0225 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0027 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0866 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0143 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030633/0424 →
SECURITY AGREEMENT Recorded Sep 3, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 024933/0316 →
SECURITY AGREEMENT Recorded Sep 3, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 024933/0340 →
SECURITY AGREEMENT Recorded Sep 1, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 024915/0759 →
SECURITY AGREEMENT Recorded Sep 1, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 024915/0777 →
SECURITY AGREEMENT Recorded May 13, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 024397/0001 →
SECURITY AGREEMENT Recorded Mar 15, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A.
Reel/Frame 024085/0001 →
SECURITY AGREEMENT Recorded Feb 2, 2007
From: FREESCALE SEMICONDUCTOR, INC.; FREESCALE ACQUISITION CORPORATION; FREESCALE ACQUISITION HOLDINGS CORP.; FREESCALE HOLDINGS (BERMUDA) III, LTD.
To: CITIBANK, N.A. AS COLLATERAL AGENT
Reel/Frame 018855/0129 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 31, 2006
From: PASSLACK, MATTHIAS; DROOPAD, RAVINDRANATH; RAJAGOPALAN, KARTHIK
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 018460/0261 →