IP Library Granted Patent US 7,494,864
Granted Patent B2
US 7,494,864 · App. 11/556,488 · Granted Feb 24, 2009

Method for production of semiconductor device

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Quick Facts
Patent No.
US 7,494,864
App. No.
11/556,488
Granted
Feb 24, 2009
Kind
B2
Abstract

A method for production of a semiconductor device including the steps of: forming a gate insulating film, a polysilicon film and a first insulating film on a silicon substrate; patterning the first insulating film; forming a metal film; forming a silicide layer by reacting the polysilicon film with the metal film; forming a second insulating film after removing an unreacted metal film; removing the second insulating film such that the first insulating film is exposed and the second insulating film remains on a region which is not covered with the first insulating film; forming a gate electrode having a silicide layer on the upper layer side and a polysilicon layer on the lower layer side by carrying out etching using the second insulating film as a mask after removing the first insulating film; forming a third insulating film on the side surface of the gate electrode; and forming an interlayer insulating film and forming a contact hole therein.

Claims (18)

1. A method for production of a semiconductor device, comprising the steps of:

forming a gate insulating film, a polysilicon film and a first insulating film on a silicon substrate;

forming on the first insulating film a mask having an opening pattern corresponding to a pattern of a gate electrode which is subsequently formed;

patterning the first insulating film by removing the first insulating film until said polysilicon film is exposed using said mask;

forming on said polysilicon film a metal film for forming a silicide;

forming a silicide layer by reacting said polysilicon film with said metal film contacting a portion not covered with the first insulating film;

removing an unreacted metal film;

forming on the polysilicon film having said silicide layer formed thereon, a second insulating film of which the etching rate is lower than that of the first insulating film in etching for removal of the first insulating film which is subsequently carried out;

removing the second insulating film such that the first insulating film is exposed and the second insulating film remains on a region which is not covered with the first insulating film;

removing the first insulating film by etching;

forming a gate electrode having a silicide layer on the upper layer side and a polysilicon layer on the lower layer side by etching said polysilicon film using the remaining second insulating film as a mask;

forming a third insulating film of which the etching rate is lower than an interlayer insulating film in etching for forming a contact hole in the interlayer insulating film which is subsequently formed, so as to cover at least the side surface of said gate electrode;

forming the interlayer insulating film; and

forming the contact hole in said interlayer insulating film by etching.

2. The method for production of a semiconductor device according to claim 1 , wherein said metal film is a cobalt film or a nickel film.

3. The method for production of a semiconductor device according to claim 1 , wherein the first insulating film is a silicon oxide film, and the second insulating film and the third insulating film are silicon nitride films.

4. The method for production of a semiconductor device according to claim 1 , wherein said contact hole is provided so as to extend to the top of silicon substrate between adjacent gate electrodes, and the opening diameter of the contact hole is larger than the minimum spacing between the gate electrodes.

5. The method for production of a semiconductor device according to claim 1 , wherein the method comprises a step of forming a side wall insulating film on the side surface of the second insulating film after the step of removing the first insulating film by etching, and in the step of forming said gate electrode, said polysilicon film is dry-etched using the side wall insulating film and the second insulating film as a mask such that said silicide layer is not exposed.

Assignments (9)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 9, 2014
From: ELPIDA MEMORY, INC.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 032645/0422 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 6, 2006
From: YOKOI, NAOKI
To: ELPIDA MEMORY, INC.
Reel/Frame 018486/0830 →