IP Library Granted Patent US 7,670,948
Granted Patent B2
US 7,670,948 · App. 11/559,724 · Granted Mar 2, 2010

Semiconductor device having diffusion barriers and a method of preventing diffusion of copper in a metal interconnection of a semiconductor device

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Quick Facts
Patent No.
US 7,670,948
App. No.
11/559,724
Granted
Mar 2, 2010
Kind
B2
Abstract

Embodiments of a semiconductor device and a method of fabricating the same may include an insulating layer formed on a substrate and having a predetermined hole, a metal interconnection formed in the hole and protruding relative to the insulating layer, a first barrier extending in a lateral direction of the metal interconnection, a second barrier formed on the metal interconnection, and a metal pad formed on the second barrier.

Claims (43)

1. A device comprising:

an insulating layer formed over a substrate, the insulating layer having a hole;

a metal interconnection formed in the hole and protruding in a direction relative to the insulating layer;

a first barrier formed over the insulating layer and extending in a lateral direction relative to the metal interconnection;

a second barrier formed over at least the metal interconnection and the first barrier; and

a metal pad formed over the second barrier,

wherein the first barrier and the second barrier each directly contact the metal interconnection.

2. The device of claim 1 , wherein the hole comprises a via hole.

3. The device of claim 1 , wherein the hole comprises a via hole and a trench communicatively coupled with the via hole.

4. The device of claim 1 , wherein the metal interconnection comprises copper.

5. The device of claim 1 , wherein the metal interconnection comprises aluminum.

6. The device of claim 1 , wherein the first barrier has a thickness in a range of approximately 100 Å to 1000 Å.

7. The device of claim 1 , further comprising a third barrier formed at a lower portion of the metal Interconnection.

8. The device of claim 7 , wherein the third barrier comprises at least one of Ta, TaN, TaAlN, TaSiN, Ti, TiN, WN, and TiSiN.

9. The device of claim 7 , wherein the third barrier comprises one of a single layer barrier and a multi-layer barrier.

10. The device of claim 1 , wherein the first barrier comprises a material substantially identical to a material forming the second barrier.

11. The device of claim 10 , wherein the first and second barriers each comprise a single layer of ruthenium oxide (RuO 2 ).

12. The device of claim 10 , wherein the first and second barriers each comprise a dual layer of ruthenium/ruthenium oxide (Ru/RuO 2 ).

13. The device of claim 1 , wherein the first barrier comprises a material different than a material forming the second barrier.

14. The device of claim 13 , wherein the first barrier comprises a single layer of ruthenium oxide (RuO 2 ).

15. The device of claim 13 , wherein the first barrier comprises a dual layer of ruthenium/ruthenium oxide (Ru/RuO 2 ).

16. The device of claim 13 , wherein the second barrier comprises at least one of Ta, TaN, TaAlN, TaSiN, Ti, TiN, WN, and TiSiN.

17. A method comprising:

forming an insulating layer having at least one hole over a substrate;

forming a metal interconnection in the at least one hole such that the metal interconnection protrudes relative to the insulating layer;

forming a first barrier over the substrate and patterning the first barrier to expose at least a portion of the metal interconnection formed in the at least one hole; and

forming a second barrier and an aluminum metal layer over the substrate and patterning the second barrier and the aluminum metal layer, to form a metal pad.

18. The method of claim 17 , wherein the first barrier extends in a lateral direction relative to the metal interconnection.

19. The method of claim 17 , wherein the metal pad is formed by sequentially etching the aluminum metal layer, the second barrier, and the first barrier.

20. The method of claim 17 , wherein forming the first barrier comprises:

forming a ruthenium (Ru) layer over the substrate; and

treating the ruthenium layer with plasma to form a ruthenium oxide (RuO 2 ) layer over a surface of the ruthenium layer.

21. The method of claim 20 , wherein the ruthenium layer is formed through a sputtering process.

22. The method of claim 20 , wherein plasma gas used for treating the ruthenium layer comprises at least one of oxygen (O 2 ) and nitrogen oxide (N 2 O).

23. The method of claim 17 , wherein the first barrier comprises a ruthenium oxide (RuO 2 ) layer formed by performing a sputtering process using ruthenium (Ru) and plasma gas.

24. The method of claim 23 , wherein the plasma comprises at least one of oxygen (O 2 ) and nitrogen oxide (N 2 O).

25. A device comprising:

an insulating layer formed over a substrate, the insulating layer having a hole;

a barrier metal layer formed in the hole;

a metal interconnection formed in the hole over and contacting the barrier metal layer and protruding from the insulating layer to form a pair of stepped areas with the uppermost surface of the insulating layer;

a first barrier formed to contact an uppermost surface of the barrier metal layer and adjacent to and contacting the metal interconnection at the stepped areas;

a second barrier formed over and contacting the metal interconnection and the first barrier; and

a metal pad formed over and contacting the second barrier.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 28, 2014
From: DONGBU HITEK CO., LTD.
To: DSS TECHNOLOGY MANAGEMENT, INC.
Reel/Frame 033035/0680 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 14, 2006
From: LEE, JAE SUK
To: DONGBU ELECTRONICS CO., LTD.
Reel/Frame 018518/0377 →