IP Library Granted Patent US 7,706,479
Granted Patent B2
US 7,706,479 · App. 11/560,508 · Granted Apr 27, 2010

OFDM receiver

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Quick Facts
Patent No.
US 7,706,479
App. No.
11/560,508
Granted
Apr 27, 2010
Kind
B2
Abstract

A carrier interpolation unit (a digital filter) performs interpolation processing of SP signal in the frequency domain. An IFFT circuit converts a frequency-domain signal into a time-domain signal. A delay profile generation unit generates a delay profile based on an output of the IFFT circuit. The filter control unit controls a pass band of the digital filter in accordance with the delay profile. An FFT window control unit controls a position of a window to extract a calculation range of FFT in accordance with the delay profile. When delay time of multipath is larger than the guard interval, and when the reception power of the interference wave is larger than a threshold, the pass band of the digital filter is minimized.

Claims (29)

1. An OFDM receiver for demodulating an OFDM signal including a pilot signal inserted in a frequency domain, comprising:

a Fourier transformation circuit for performing Fourier transformation of the OFDM signal;

a delay profile circuit for generating a delay profile of the pilot signal extracted from an output signal of said Fourier transformation circuit;

an interpolation circuit for performing interpolation processing of the pilot signal extracted from the output signal of said Fourier transformation circuit in the frequency domain;

a filter control circuit for controlling a filter characteristic of said interpolation circuit based on the delay profile; and

a correction circuit for correcting a data signal extracted from the output signal of said Fourier transformation circuit using an output of said interpolation circuit, wherein

the filter control circuit compares a guard interval of OFDM with a time lag between a main wave and an interference wave, determines whether the time lag is larger than the guard interval, calculates a power ratio of the main wave and the interference wave when the time lag is larger than the guard interval, and controls the filter characteristic of said interpolation circuit in accordance with the calculated power ratio of the main wave and the interference wave.

2. The OFDM receiver according to claim 1 , wherein

said interpolation circuit comprises an FIR filter, and

said filter control circuit controls a pass band by adjusting a tap coefficient of the FIR filter.

3. The OFDM receiver according to claim 1 , wherein

said filter control circuit, when the time lag between the main wave and the interference wave is larger than the guard interval of OFDM, and when the power ratio of the main wave to the interference wave is less than a threshold, controls the filter characteristic to pass the main wave and to remove the interference wave.

4. The OFDM receiver according to claim 1 , wherein

said filter control circuit, when the time lag between the main wave and the interference wave is larger than the guard interval of OFDM, and when the power ratio of the main wave to the interference wave is more than a threshold, controls the filter characteristic to pass both of the main wave and the interference wave.

5. The OFDM receiver according to claim 1 , further comprising:

a window control circuit for controlling a position of a window to extract a calculation range in said Fourier transformation circuit using the delay profile.

6. The OFDM receiver according to claim 5 , wherein

said window control circuit, when the time lag between the main wave and the interference wave is larger than the guard interval of OFDM, and when the power ratio of the main wave to the interference wave is less than a threshold, sets the window so as to extract the main wave.

7. The OFDM receiver according to claim 5 , wherein

said window control circuit, when the time lag between the main wave and a delay interference wave is larger than the guard interval of OFDM, and when the power ratio of the main wave to the delay interference wave is more than a threshold, sets the window so as to extract the main wave.

8. The OFDM receiver according to claim 5 , wherein the window control circuit, when the time lag between the main wave and a preceding interference wave is larger than the guard interval of OFDM, and when the power ratio of the main wave to the preceding interference wave is more than a threshold, sets the window so as to extract the preceding interference wave.

9. The OFDM receiver according to claim 1 , wherein

the pilot signal is a scattered pilot signal of digital terrestrial broadcasts.

10. A equalization method for equalizing a data signal in an OFDM receiver for demodulating an OFDM signal including a pilot signal inserted in a frequency domain, comprising:

performing Fourier transformation of the OFDM signal using a Fourier transformation circuit;

generating a delay profile of the pilot signal extracted from an output signal of the Fourier transformation circuit;

performing interpolation processing of the pilot signal extracted from the output signal of the Fourier transformation circuit in the frequency domain based on the delay profile;

comparing a guard interval of OFDM with a time lag between a main wave and an interference wave, determining whether the time lag is larger than the guard interval, calculating a power ratio of the main wave and the interference wave when the time lag is larger than the guard interval, and controlling a filter characteristic for the interpolation processing in accordance with the calculated power ratio of the main wave to the interference wave; and

correcting and outputting the data signal extracted from the output signal of the Fourier transformation circuit using information obtained by the interpolation processing.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 27, 2015
From: FUJITSU SEMICONDUCTOR LIMITED
To: SOCIONEXT INC.
Reel/Frame 035508/0637 →
CHANGE OF NAME Recorded Jul 27, 2010
From: FUJITSU MICROELECTRONICS LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 024794/0500 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 10, 2008
From: FUJITSU LIMITED
To: FUJITSU MICROELECTRONICS LIMITED
Reel/Frame 021985/0715 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 16, 2006
From: ADACHI, NAOTO
To: FUJITSU LIMITED
Reel/Frame 018609/0170 →