Memory device having concurrent write and read cycles and method thereof
View Patent ↗A memory device includes a latch having an input to receive a bit value, an input to receive a clock signal, and an output to provide a latched bit value based on the clock signal. The memory device further includes a bit cell including a storage component, and a write row driver configured to enable write access to the bit cell to store the latched bit value at the storage component for a first phase and a second phase of a cycle of the clock signal, the second phase following the first phase, and a read row driver configured to disable read access to the bit cell for the first phase of the cycle of the clock signal and to enable read access to the bit cell for the second phase of the cycle of the clock signal.
1. A method comprising:
receiving, at a memory device, a first bit value to be stored at a first bit cell;
latching the first bit value to generate a latched first bit value;
enabling, for a first phase and a second phase of a first cycle of a clock signal, a write access to store the first bit value at the first bit cell based on the latched first bit value, wherein the second phase follows the first phase; and
enabling, for the second phase of the first cycle of the clock signal, a read access to the first bit cell.
2. The method of claim 1 , wherein enabling the write access comprises:
determining a write word line associated with the first bit cell based on a write address value; and
asserting the write word line in response to a first edge event of the clock signal, wherein the first bit cell is enabled to store a bit value in response to the write word line being asserted and wherein the first edge event indicates an initiation of the first phase of the first cycle of the clock signal; and
deasserting the write word line in response to a second edge event of the clock signal, wherein the first bit cell is disabled from storing a bit value in response to the write word line being deasserted and wherein the second edge event indicates a termination of the second phase of the first cycle of the clock signal.
3. The method of claim 2 , further comprising:
latching the write address value to generate a latched write address value for the first cycle of the clock signal;
wherein latching the first bit value comprises latching the first bit value for the first cycle of the clock signal.
4. The method of claim 2 , wherein enabling the read access to the first bit cell comprises:
determining a read word line associated with the read access based on a read address value associated with the read access;
asserting the read word line in response to a third edge event of the clock signal, wherein the first bit cell is enabled to output a bit value in response to the read word line being asserted and wherein the third edge event indicates an initiation of the second phase of the first cycle of the clock signal; and
deasserting the read word line in response to the second edge event of the clock signal, wherein the first bit cell is disabled from outputting a bit value in response to the read word line being deasserted.
5. The method of claim 1 , further comprising:
sensing the first bit value at the first bit cell during the read access.
6. The method of claim 1 , further comprising:
receiving, at the memory device, a second bit value to be stored at a second bit cell;
latching the second bit value to generate a latched second bit value;
enabling, for a first phase and a second phase of a second cycle of the clock signal, a write access to store the second bit value at the second bit cell based on the latched second bit value, wherein the second phase follows the first phase; and
enabling, for the second phase of the second cycle of the clock signal, a read access to the second bit cell.
7. The method of claim 6 , further comprising:
determining a first write word line associated with the first bit cell based on a first write address value;
asserting the first write word line in response to a first edge event of the clock signal, wherein the first bit cell is enabled to store a bit value in response to the first write word line being asserted and wherein the first edge event indicates an initiation of the first phase of the first cycle of the clock signal;
deasserting the first write word line in response to a second edge event of the clock signal, wherein the first bit cell is disabled from storing a bit value in response to the first write word line being disabled and wherein the second edge event indicates a termination of the second phase of the first cycle of the clock signal;
determining a second write word line associated with the second bit cell based on a second write address value;
asserting the second write word line in response to a third edge event of the clock signal, wherein the second bit cell is enabled to store a bit value in response to the second write word line being asserted and wherein the third edge event indicates an initiation of the first phase of the second cycle of the clock signal; and
deasserting the second write word line in response to a fourth edge event of the clock signal, wherein the second bit cell is disabled from storing a bit value in response to the second write word line being deasserted and wherein the fourth edge event indicates a termination of the second phase of the second cycle of the clock signal.
8. A memory device comprising:
a first latch having an input to receive a bit value, an input to receive a clock signal, and an output to provide a latched bit value based on the clock signal;
a bit cell comprising a storage component;
a write row driver configured to enable write access to the bit cell to store the latched bit value at the storage component for a first phase and a second phase of a cycle of the clock signal, the second phase following the first phase; and
a read row driver configured to disable read access to the bit cell for the first phase of the cycle of the clock signal and to enable read access to the bit cell for the second phase of the cycle of the clock signal.
9. The memory device of claim 8 , further comprising:
a second latch having an input to receive a write enable signal, an input to receive the clock signal, and an output to provide a latched write enable signal for the first phase and the second phase of the cycle of the clock signal; and
wherein the write row driver is configured to enable write access to the bit cell in response to the latched write enable signal having a first state and disable write access to the bit cell in response to the latched write enable signal having a second state.
10. The memory device of claim 9 , wherein the read row driver comprises an input to receive a read enable signal, the read enable signal having the second state for the first phase of the cycle of the clock signal and having the first state for the second phase of the cycle of the clock signal, and wherein the read row driver is configured to disable read access to the bit cell in response to the read enable signal having the second state and to enable read access to the bit cell in response to the read enable signal having the first state.
11. The memory device of claim 9 , wherein the read row driver comprises an input to receive a read enable signal, the read enable signal having the second state for the first phase of the cycle of the clock signal and having the first state for the second phase of the cycle of the clock signal, and wherein the read row driver is configured to disable read access to the bit cell in response to the read enable signal having the first state and to enable read access to the bit cell in response to the read enable signal having the second state.
12. The memory device of claim 8 , wherein the bit cell comprises a first input coupled to a write word line, a second input coupled to a read word line, a third input coupled to the output of the first latch, and an output, wherein the bit cell is configured to store to the storage component a bit value at the third input in response to the write word line being asserted and to provide a bit value stored at the storage component to the output in response to the read word line being asserted.
13. The memory device of claim 12 , wherein:
the write row driver is configured to assert the write word line for the first phase and the second phase; and
the read row driver is configured to deassert the read word line for the first phase and to assert the read word line for the second phase.
14. The memory device of claim 13 , further comprising:
a latch to receive a write address value associated with the first bit cell, an input to receive the clock signal, and an output to provide a latched write address value; and
wherein the write row driver is configured to select the write word line from a plurality of write word lines based on the latched write address value.
15. The memory device of claim 12 , wherein the bit cell comprises:
a first inverter having an input connected to a first node and an output connected to a second node;
a second inverter having an input connected to the second node and an output connected to the first node, wherein the storage component comprises the first inverter and the second inverter;
a first transistor comprising a first current electrode connected to the third input, a second current electrode connected to the first node, and a control electrode connected to the write word line;
a second transistor comprising a first current electrode connected to a read bit line, a second current electrode, and a control electrode connected to the read word line; and
a third transistor comprising a first current electrode connected to a voltage reference, a second current electrode connected to the second current electrode of the second transistor, and a control electrode connected to the second node.
16. The memory device of claim 15 , wherein the bit cell further comprises:
a third inverter comprising an input coupled to the second node and an output coupled to the control electrode of the third transistor, wherein the control electrode of the third transistor is coupled to the second node via the third inverter.
17. The memory device of claim 8 , further comprising an array of bit cells including the bit cell, each of the bit cells of the array including a storage component.
18. A memory device comprising:
a first latch having an input to receive a bit value, an input to receive a clock signal, and an output to provide a latched bit value based on the bit value for a first phase and a second phase of a cycle of the clock signal, wherein the second phase follows the first phase;
a second latch having an input configured to receive a write enable signal, an input to receive the clock signal, and an output to provide a latched write enable signal for the first phase and the second phase;
a write row driver having an input to receive the latched write enable signal, the write row driver configured to assert a write word line in response to the latched write enable signal having a first state and to deassert the write word line in response to the latched write enable signal having a second state;
a read row driver having an input to receive a read enable signal, the read row driver configured to assert a read word line in response to the read enable signal having a first state and to deassert the read word line in response to the read enable signal having a second state; and
a bit cell array comprising a bit cell configured to selectively enable write access to the bit cell based on a state of the write word line and selectively enable read access to the bit cell based on a state of the read word line.
19. The memory device of claim 18 , further comprising:
a second latch to receive a write address value associated with the bit cell, an input to receive the clock signal, and an output to provide a latched write address value; and
wherein the write row driver is configured to select the write word line from a plurality of write word lines based on the latched write address value.
20. The memory device of claim 18 , wherein the bit cell comprises a storage component, a first input coupled to the write word line, a second input coupled to the read word line, a third input coupled to the output of the first latch, and an output, and wherein the bit cell is configured to store to the storage component a bit value at the third input in response to the write word line being asserted and to provide a bit value stored at the storage component to the output in response to the read word line being asserted.