IP Library Granted Patent US 7,463,012
Granted Patent B2
US 7,463,012 · App. 11/561,875 · Granted Dec 9, 2008

Bandgap reference circuits with isolated trim elements

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Quick Facts
Patent No.
US 7,463,012
App. No.
11/561,875
Granted
Dec 9, 2008
Kind
B2
Abstract

A bandgap reference circuit utilizes differential transistors to generate a temperature-independent bandgap voltage. In place of conventional trim elements that are connected in parallel to and adjust the resistance values of the bandgap reference circuit, current control circuits are placed in the current paths passing through the differential transistors (i.e., connected to the critical nodes located at the terminals of the differential transistors). Each current control circuit includes a resistive “trim” element (e.g., a zener diode) and associated trim pads that are separated from the critical nodes (i.e., the terminals of the differential transistors) by isolation transistors such that, during a trim/test procedure, the stray capacitances introduced by trim/test equipment probes are prevented from altering the performance of the bandgap reference circuit. In one embodiment, a current control circuit is connected to the critical node connected to the base of at least one of the differential transistors.

Claims (32)

1. A bandgap reference circuit for generating a temperature-independent bandgap voltage, the bandgap reference circuit comprising:

first and second differential transistors, the first differential transistor having a first, relatively small size and operating at a relatively small emitter current density, and the second differential transistor having a second, relatively large size and operating at a relatively large emitter current density, wherein each terminal of said first and second differential transistors defines a critical node; and

at least one current control circuit connected to at least one critical node of at least one of said first and second differential transistors, wherein said at least one current control circuit includes:

an isolation transistor having a first terminal connected to said at least one critical node, a gate terminal connected to a predetermined control voltage, and a second terminal;

a trim element having a first terminal connected to the second terminal of the isolation transistor, and a second terminal connected to the ground node; and

first and second trim pads respectively connected to the first and second terminals of the trim element,

wherein the trim element is formed such that a current above a predetermined level that is generated between the first trim pad and the second trim pad changes a resistance value of said trim element.

2. The bandgap reference circuit according to claim 1 ,

wherein a first critical node is defined at a terminal of the first differential transistor,

wherein a second critical node is defined at a terminal of the second differential transistor, and

wherein said at least one current control circuit comprises:

a first current control circuit connected between the first critical node and the ground node, and

a second current control circuit connected between the second critical node and the ground node.

3. The bandgap reference circuit according to claim 2 , further comprising an amplifier having a first terminal connected to the first critical node, and a second terminal connected to the second critical node, wherein the temperature-independent bandgap voltage is generated at an output terminal of the amplifier.

4. The bandgap reference circuit according to claim 3 , further comprising a first resistor having a first terminal defining a third critical node that is connected to the output terminal of the amplifier and to a base of the first differential transistor, and a second terminal defining a fourth critical node that is connected to a base of the second differential transistor.

5. The bandgap reference circuit according to claim 4 , further comprising a second resistor and a diode connected in series between the second terminal of the first resistor and the ground node.

6. The bandgap reference circuit according to claim 4 , further comprising a third current control circuit connected between one of the third and fourth critical nodes and the ground node.

7. The bandgap reference circuit according to claim 1 ,

wherein a base of the second differential transistor defines a third critical node,

wherein a base of the first differential transistor defines a fourth critical node, and

wherein said at least one current control circuit is connected to at least one of the third critical node and the fourth critical node.

8. The bandgap reference circuit according to claim 1 , wherein each trim element comprises a zener diode.

9. The bandgap reference circuit according to claim 1 , wherein said at least one current control circuit comprises at least one of:

a first isolation transistor and a first trim element connected in series between a first critical node defined by a collector terminal of the first differential transistor;

a second isolation transistor and a second trim element connected in series between a second critical node defined by a collector terminal of the second differential transistor; and

a third isolation transistor and a third trim element connected in series between one of a third critical node defined by a base terminal of the first differential transistor and a fourth critical node defined by a base terminal of the second differential transistor.

10. The bandgap reference circuit according to claim 9 , wherein said at least one current control circuit further comprises a current source comprising a transistor having a source terminal and a gate terminal connected to the fourth critical node, and a drain terminal connected to the ground node.

11. The bandgap reference circuit according to claim 9 ,

wherein the first and second differential transistors are connected to a current mirror,

wherein the first critical node is defined between the first differential transistor and the current mirror, and the second critical node is defined between the first differential transistor and the current mirror,

wherein the bandgap reference circuit further comprises an amplifier having an input terminal connected to the second critical node, said amplifier generating said temperature-independent bandgap voltage at an output terminal, and

wherein said current mirror is connected between the output terminal of the amplifier and the first and second critical nodes.

Assignments (10)
INTELLECTUAL PROPERTY BUY-IN AGREEMENT/ASSIGNMENT Recorded Apr 4, 2023
From: MICREL LLC
To: MICROCHIP TECHNOLOGY INCORPORATED
Reel/Frame 063241/0771 →
RELEASE OF SECURITY INTEREST Recorded Mar 14, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 060894/0437 →
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059363/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 10, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059863/0400 →
SECURITY INTEREST Recorded Jun 4, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 057935/0474 →
SECURITY INTEREST Recorded Dec 24, 2020
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 055671/0612 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 053468/0705 →
RELEASE OF SECURITY INTEREST Recorded May 30, 2020
From: JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 053466/0011 →
SECURITY INTEREST Recorded Apr 24, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 053311/0305 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 20, 2006
From: MOTTOLA, MICHAEL J.
To: MICREL, INCORPORATED
Reel/Frame 018539/0804 →