P-channel NAND in isolated N-well
View Patent ↗A device includes a substrate and multiple wells formed over the substrate and isolated from one another by dielectric trenches. The device further includes multiple memory elements formed over the wells, each of the memory elements extending approximately perpendicular to the wells and including a material doped with n-type impurities. The device also includes multiple source/drain regions, each source/drain region formed within one of multiple trenches and inside one of the plurality of wells between a pair of the memory elements, each of the source/drain regions implanted with p-type impurities. The device further includes a first substrate contact formed in a first one of the multiple trenches through a first one of the wells into the substrate and a second substrate contact formed in a second one of the multiple trenches through a second one of the wells into the substrate.
1. A device, comprising:
a plurality of columns, each of the columns comprising an oxide-nitride-oxide (ONO) stack and a layer of material formed over the ONO stack and separated from one another by a plurality of first trenches; and
a plurality of wells formed beneath, and transverse to, the plurality of columns, each of the wells comprising a semiconducting material doped with n-type impurities and being separated from one another by second trenches of dielectric material;
a substrate layer formed beneath the plurality of wells;
a first substrate contact formed in a first one of the plurality of first trenches through the ONO stack and through a first one of the plurality of wells into the substrate layer; and
a second substrate contact formed in a second one of the plurality of first trenches through the ONO stack and through a second one of the plurality of wells into the substrate layer.
2. The device of claim 1 , where the ONO stack has a thickness ranging from about 90 Å to about 400 Å.
3. The device of claim 1 , where the layer of material comprises a semiconducting material or a metal.
4. The device of claim 3 , where the semiconducting material comprises polycrystalline silicon and where the metal comprises tantalum nitride or titanium nitride.
5. The device of claim 4 , where the layer of material has a thickness ranging from about 200 Å to about 2,000 Å.
6. The device of claim 1 , where the first and second substrate contacts comprise regions of semiconducting material doped with p-type impurities.
7. The device of claim 1 , further comprising:
a plurality of contacts, each of the plurality of contacts formed to connect with a respective one of the plurality of wells through a respective one of the plurality of first trenches.
8. The device of claim 1 , further comprising:
implantation regions formed within the plurality of first trenches, the implantation regions comprising semiconducting material implanted with impurities.
9. The device of claim 8 , where the impurities comprise p-type impurities.
10. The device of claim 8 , where the implantation regions form source or drain regions for each of the plurality of columns.
11. The device of claim 1 , further comprising:
spacers formed within each of the plurality of first trenches adjacent sidewalls of each of the plurality of columns.
12. A device, comprising:
a substrate;
a plurality of wells formed over the substrate and isolated from one another by dielectric trenches, where the plurality of wells comprise a material doped with n-type impurities;
a plurality of memory elements formed over the plurality of wells, each of the memory elements extending approximately perpendicular to the plurality of wells;
a plurality of source/drain regions, each source/drain region formed within one of a plurality of trenches and inside one of the plurality of wells between a pair of the plurality of memory elements, each of the plurality of source/drain regions implanted with p-type impurities;
a first substrate contact formed in a first one of the plurality of trenches through a first one of the plurality of wells into the substrate; and
a second substrate contact formed in a second one of the plurality of trenches through a second one of the plurality of wells into the substrate.
13. The device of claim 12 , where the first and second substrate contacts are doped with p-type impurities.
14. The device of claim 12 , where each of the plurality of memory elements comprises a layer of semiconducting or metal material formed over an oxide-nitride-oxide (ONO) stack.
15. The device of claim 14 , where the ONO stack has a thickness ranging from about 90 Å to about 400 Å.
16. The device of claim 12 , where each of the dielectric trenches comprises a liner and a dielectric material formed in each trench.
17. The device of claim 16 , where each trench of the dielectric trenches is formed to a depth of approximately 3,600 Å.
18. The device of claim 12 , further comprising:
spacers formed within each of the plurality of first trenches adjacent sidewalls of the memory elements.
19. A device, comprising:
a plurality of columns, each of the columns comprising an oxide-nitride-oxide (ONO) stack and a layer of material formed over the ONO stack and separated from one another by a plurality of first trenches;
a plurality of wells formed beneath, and transverse to, the plurality of columns, each of the wells comprising a semiconducting material doped with n-type impurities and being separated from one another by second trenches of dielectric material; and
a plurality of contacts, each of the plurality of contacts formed to connect with a respective one of the plurality of wells through a respective one of the plurality of first trenches.