IP Library Granted Patent US 7,430,147
Granted Patent B2
US 7,430,147 · App. 11/584,642 · Granted Sep 30, 2008

Precharge apparatus

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Quick Facts
Patent No.
US 7,430,147
App. No.
11/584,642
Granted
Sep 30, 2008
Kind
B2
Abstract

A precharge circuit prevents voltage dropping of a local input/output line in a semiconductor memory apparatus. The precharge circuit includes at least one pair of pull-up and pull-down precharge circuits. When a local input/output line precharge signal is enabled, a precharge voltage to be applied to each of the precharge circuits is supplied to a local input/output line and a local input/output line-bar. The pull-up precharge circuit has P-type MOS transistors, and the pull-down precharge circuit has N-type transistors. With this configuration, dropping of precharge voltage levels of local input/output lines can be prevented, thus improving reliability of the memory apparatus.

Claims (70)

1. A precharge apparatus, comprising:

at least one pair of pull-up and pull-down precharge circuits,

wherein, when a local input/output line precharge signal is enabled, the pull-down precharge circuit and the pull-up precharge circuit are respectively driven in response to a synchronizing local input/output line precharge signal and a synchronizing local input/output line precharge-bar signal generated from the local input/output line precharge signal by skew-adjusting, and a precharge voltage to be applied to each of the precharge circuits is supplied to a local input/output line and a local input/output line-bar.

2. The precharge apparatus of claim 1 , wherein the pull-up precharge circuit includes P-type MOS transistors, and the pull-down precharge circuit includes N-type MOS transistors.

3. The precharge apparatus of claim 1 , further comprising:

a first synchronization section which receives the local input/output line precharge signal and outputs the synchronizing local input/output line precharge signal so as to drive one of the pair of precharge circuits; and

a second synchronization section which receives the local input/output line precharge signal and outputs the synchronizing local input/output line precharge-bar signal having an opposite phase to the synchronizing local input/output line precharge signal so as to drive the other precharge circuit.

4. The precharge apparatus of claim 3 , wherein

the pair of precharge circuits includes a precharge circuit having pull-down MOS transistors and a precharge circuit having pull-up MOS transistors, and

the synchronizing local input/output line precharge signal output from the first synchronization section is a driving signal of the precharge circuit having the pull-down MOS transistors.

5. The precharge apparatus of claim 3 , wherein:

the pair of precharge circuits includes a precharge circuit having pull-down MOS transistors and a precharge circuit having pull-up MOS transistors, and

the synchronizing local input/output line precharge-bar signal output from the second synchronization section is a driving signal of the precharge circuit having pull-up MOS transistors.

6. The precharge apparatus of claim 3 , wherein

the first synchronization section includes:

an inverter group which receives the local input/output line precharge signal, and

a skew correction section which receives an output signal of the inverter group and outputs the synchronizing local input/output line precharge signal.

7. The precharge apparatus of claim 3 , wherein the second synchronization section includes:

an inverter group which receives the local input/output line precharge signal, and

a skew correction section which receives an output signal of the inverter group and outputs the synchronizing local input/output line precharge-bar signal.

8. The precharge apparatus of claim 6 , wherein the inverter group includes an even number of CMOS inverters connected in series.

9. The precharge apparatus of claim 6 , wherein the skew correction section includes an even number of inversion elements connected in series.

10. The precharge apparatus of claim 7 , wherein the inverter group includes an odd number of CMOS inverters connected in series.

11. The precharge apparatus of claim 7 , wherein the skew correction section includes an even number of inversion elements connected in series.

12. The precharge apparatus of claim 7 , wherein the second synchronization section further includes a pulse-width adjusting unit which is connected to an output terminal of the skew correction section so as to control a pulse width of a signal output from the skew correction section.

13. A precharge apparatus, comprising:

a precharge section which has at least one pair of precharge circuits to be simultaneously driven by a synchronizing local input/output line precharge signal and a synchronizing local input/output line precharge-bar signal, generated from a local input/output line precharge signal by skew-adjusting, having opposing phases generated when the local input/output line precharge signal is enabled, and supplies a bit line precharge voltage to be applied to each of the precharge circuits to a local input/output line and a local input/output line-bar.

14. The precharge apparatus of claim 13 , wherein the precharge section includes:

a first precharge circuit which is driven by the synchronizing local input/output line precharge signal and supplies the bit line precharge voltage to the local input/output line and the local input/output line-bar, and

a second precharge circuit which is driven by the synchronizing local input/output line precharge-bar signal and supplies the bit line precharge voltage to the local input/output line and the local input/output line-bar.

15. The precharge apparatus of claim 14 , wherein the first precharge circuit includes:

a first MOS transistor which is connected between the local input/output line and a bit line precharge voltage input terminal,

a second MOS transistor which is connected between the bit line precharge voltage input terminal and the local input/output line-bar, and

a third MOS transistor which is connected between the local input/output line and the local input/output line-bar,

each of the first to third MOS transistors is driven by the synchronizing local input/output line precharge signal.

16. The precharge apparatus of claim 15 , wherein the first to third MOS transistors are pull-down MOS transistors.

17. The precharge apparatus of claim 14 , wherein the second precharge circuit includes:

a first MOS transistor which is connected between the local input/output line and the bit line precharge voltage input terminal,

a second MOS transistor which is connected between the bit line precharge voltage input terminal and the local input/output line-bar, and

a third MOS transistor which is connected between the local input/output line and the local input/output line-bar,

each of the first to third MOS transistors is driven by the synchronizing local input/output line precharge-bar signal.

18. The precharge apparatus of claim 17 , wherein the first to third MOS transistors are pull-up MOS transistors.

19. The precharge apparatus of claim 13 , further comprising:

a first synchronization section which receives the local input/output line precharge signal and outputs the synchronizing local input/output line precharge signal; and

a second synchronization section which receives the local input/output line precharge signal and outputs the synchronizing local input/output line precharge-bar signal having an opposite phase to the output signal of the first synchronization section.

20. The precharge apparatus of claim 19 , wherein the first synchronization section includes:

an inverter group which receives the local input/output line precharge signal, and

a skew correction section which receives an output signal of the inverter group and outputs the synchronizing local input/output line precharge signal.

21. The precharge apparatus of claim 20 , wherein the inverter group includes an even number of CMOS inverters connected in series.

22. The precharge apparatus of claim 20 , wherein the skew correction section includes an even number of inversion elements connected in series.

23. The precharge apparatus of claim 19 , wherein the second synchronization section includes:

an inverter group which receives the local input/output line precharge signal, and

a skew correction section which receives an output signal of the inverter group and outputs the synchronizing local input/output line precharge-bar signal.

24. The precharge apparatus of claim 23 , wherein the inverter group includes an odd number of CMOS inverters connected in series.

25. The precharge apparatus of claim 23 , wherein the skew correction section includes an even number of inversion elements connected in series.

26. The precharge apparatus of claim 23 , wherein the second synchronization section further includes a pulse-width adjusting unit which is connected to an output terminal of the skew correction section so as to control a pulse width of a signal output from the skew correction section.

27. A precharge apparatus, comprising:

at least one pair of pull-up and pull-down precharge circuits, and

at least one pair of a synchronizing local input/output line precharge signal and a synchronizing local input/output line precharge-bar signal generated from a local input/output line precharge signal by skew-adjusting,

wherein, when the local input/output line precharge signal is enabled, the pull-down and the pull-up precharge circuits are respectively driven in response to the synchronizing local input/output line precharge signal and the synchronizing local input/output line precharge-bar signal.

28. The precharge apparatus of claim 27 further comprises:

a first synchronization section which receives the local input/output line precharge signal and outputs the synchronization local input/output precharge signal so as to drive a first of the pair of precharge circuits; and

a second synchronization section which receives the local input/output line precharge signal and outputs the synchronization local input/output line precharge-bar signal having an opposite phase to the synchronization local input/output line precharge signal, so as to drive a second of the pair of precharge circuits.

29. The precharge apparatus of claim 28 , wherein

the first synchronization section includes:

an inverter group which receives the local input/output line precharge signal, and

a skew correction section which receives an output signal of the inverter group and outputs the synchronizing local input/output line precharge signal.

30. The precharge apparatus of claim 28 , wherein the second synchronization section includes:

an inverter group which receives the local input/output line precharge signal, and

a skew correction section which receives an output signal of the inverter group and outputs the synchronizing local input/output line precharge-bar signal.

Assignments (4)
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE IS HYNIX SEMICONDUCTOR INC. NOT HYNIX-SEMICONDUCTOR INC. THERE IS NO HYPHEN IN THE NAME. PREVIOUSLY RECORDED ON REEL 67328 FRAME 814. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME. Recorded May 14, 2024
From: HYNIX SEMICONDUCTOR INC.
To: SK HYNIX INC.
Reel/Frame 067412/0482 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 9, 2024
From: SK HYNIX INC.
To: MIMIRIP LLC
Reel/Frame 067369/0832 →
CHANGE OF NAME Recorded May 6, 2024
From: HYNIX-SEMICONDUCTOR INC.
To: SK HYNIX INC.
Reel/Frame 067328/0814 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 23, 2006
From: KWACK, SEUNG-WOOK
To: HYNIX SEMICONDUCTOR INC.
Reel/Frame 018448/0118 →