IP Library Granted Patent US 7,589,024
Granted Patent B2
US 7,589,024 · App. 11/594,746 · Granted Sep 15, 2009

Process for producing semiconductor integrated circuit device

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Quick Facts
Patent No.
US 7,589,024
App. No.
11/594,746
Granted
Sep 15, 2009
Kind
B2
Abstract

Recently, with shortened wavelengths employed in aligners, it is now difficult to use a material containing a benzene ring as a photoresist material. Since resist has extremely low plasma resistance, formation of deep holes using a photoresist as a dry etching mask is difficult. Under such circumstances, in the present invention, amorphous carbon film 6 is formed on photoresist 4 in which first hole 5 is formed, and using amorphous carbon film 6 as a mask, deep second hole 7 is formed in a etch target material such as underlying SiO 2 film 2.

Claims (43)

1. A process for producing a semiconductor integrated circuit device, said process comprising:

forming a photoresist film on an etch target material,

forming a first hole comprising patterning said photoresist film such that a surface of said etch target material is exposed,

depositing an amorphous carbon film on said photoresist film and a side wall of said first hole to have a film thickness of said amorphous carbon film such that said first hole is not filled with said amorphous carbon film and a diameter of an upper portion of said first hole is less than a diameter of a lower portion of said first hole, and

forming a second hole in said etch target material, said forming said second hole comprising using one of said amorphous carbon film and a combination of said amorphous carbon film and said photoresist film as a mask.

2. The process for producing a semiconductor integrated circuit device according to claim 1 , wherein said depositing said amorphous carbon film comprises using a plasma chemical vapor deposition (CVD) method.

3. The process for producing a semiconductor integrated circuit device according to claim 1 , further comprising:

forming an antireflection film between said etch target material and said photoresist film,

wherein said forming said first hole further comprises:

forming a predetermined hole in said photoresist film; and

removing the antireflection film exposed at a bottom portion of said predetermined hole after said forming said predetermined hole.

4. The process for producing a semiconductor integrated circuit device according to claim 1 , wherein said depositing said amorphous carbon film comprises forming said amorphous carbon film by chemical vapor deposition (CVD), and

wherein said CVD uses a raw material gas selected from a group consisting of acetylene, propene, butane, methane, ethane, propane, and butane in said forming said amorphous carbon film.

5. The process for producing a semiconductor integrated circuit device according to claim 1 , wherein said film thickness of said amorphous carbon film is less than one-half of a diameter of said first hole.

6. The process for producing a semiconductor integrated circuit device according to claim 5 , wherein said film thickness of said amorphous carbon film is greater than or equal to 1 nm.

7. The process for producing a semiconductor integrated circuit device according to claim 1 , wherein said depositing said amorphous carbon film comprises depositing said amorphous carbon film on said exposed surface of said etch target material.

8. The process for producing a semiconductor integrated circuit device according to claim 1 , wherein said amorphous carbon film consists essentially of amorphous carbon.

9. The process for producing a semiconductor integrated circuit device according to claim 1 , wherein said depositing said amorphous carbon film comprises using one of sputtering and chemical vapor deposition (CVD).

10. A process for producing a semiconductor integrated circuit device, said process comprising:

forming a photoresist film on an etch target material;

forming a first hole having an aspect ratio of 1.8 or greater, said forming said first hole comprising patterning said photoresist film such that a surface of said etch target material is exposed;

depositing an amorphous carbon film on said photoresist film and a side wall of said first hole to have a film thickness of said amorphous carbon film such that said first hole is not filled with said amorphous carbon film and a diameter of an upper portion of said first hole is less than a diameter of a lower portion of said first hole; and

forming a second hole in said etch target material, said forming said second hole comprising using one of said amorphous carbon film and a combination of said amorphous carbon film and said photoresist film as a mask.

11. The process for producing a semiconductor integrated circuit device according claim 10 , wherein said amorphous carbon film is not deposited on said exposed surface of said etch target material.

12. A process for producing a semiconductor integrated circuit device, said process comprising:

forming a photoresist film on an insulating film formed on a substrate;

forming a first hole comprising patterning said photoresist film such that a surface of said insulating film is exposed;

depositing an amorphous carbon film on said photoresist film and a side wall of said first hole to have a film thickness of said amorphous carbon film such that said first hole is not filled with said amorphous carbon film and a diameter of an upper portion of said first hole is less than a diameter of a lower portion of said first hole; and

forming a second hole in said insulating film, said forming said second hole comprising using one of said amorphous carbon film and a combination of said amorphous carbon film and said photoresist film as a mask.

13. The process for producing a semiconductor integrated circuit device according to claim 12 , wherein said insulating film comprises one of a silicon dioxide film, a silicon nitride film, a silicon oxynitride film, a methylsiloxane insulating film, porous SiOC, and porous SiOCH.

14. The process for producing a semiconductor integrated circuit device according to claim 12 , wherein said forming said second hole further comprises extending said second hole to said substrate such that said second hole does not include said substrate.

15. The process for producing a semiconductor integrated circuit device according to claim 12 , wherein said depositing said amorphous carbon film is conducted when an RF power is in a range from 200 W to 800 W and said substrate has a temperature in a range from 80° C. to 100° C.

16. A process for producing a semiconductor integrated circuit device, said process comprising:

forming a sacrificial hard mask layer on an insulating film formed on a substrate,

forming a photoresist film on said sacrificial hard mask layer,

forming a patterning hole comprising patterning said photoresist film such that a surface of said sacrificial hard mask layer is exposed on said insulating film,

depositing an amorphous carbon film on said photoresist film and a side wall of said patterning hole to have a film thickness of said amorphous carbon film such that said patterning hole is not filled with said amorphous carbon film and a diameter of an upper portion of said patterning hole is less than a diameter of a lower portion of said patterning hole,

forming a mask hole in said sacrificial hard mask layer, said forming said mask hole comprising using one of said amorphous carbon film and a combination of said amorphous carbon film and said photoresist film as a mask,

forming an insulating hole in said insulating film through the mask hole,

filling said insulating hole with a resist after said forming said insulating hole, and

removing said sacrificial hard mask layer remaining on the insulating film after said filling said insulating hole.

17. The process for producing a semiconductor integrated circuit device according to claim 16 , wherein said insulating film comprises a silicon dioxide film, and

wherein said forming said sacrificial hard mask layer comprises forming a polysilicon film.

Assignments (9)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 9, 2014
From: ELPIDA MEMORY, INC.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 032645/0422 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 9, 2006
From: UEDA, YASUHIKO
To: ELPIDA MEMORY, INC.
Reel/Frame 018538/0768 →