ESD protection circuit

1. An Electro-Static Discharge (ESD) protection circuit, comprising:

a detection unit for detecting a rising time of a signal flowing into first and second power lines;

a pre-driver including two or more second inverters for buffering an output signal of the detection unit; and

a power clamp which operates in response to an output signal of the pre-driver and connects the first and second power lines with each other, wherein the detection unit includes:

an RC filter connected in series between the first and the second power lines;

a first inverter for inverting an output of the RC filter; and

a first capacitor, directly connected between the first power line and a first transistor of the first inverter, for preventing a leakage current flowing through the first transistor and a second transistor of the first inverter when a power noise is applied to the first and second power lines.

2. The ESD protection circuit as recited in claim 1 , wherein the RC filter is composed of a first resistor and a second capacitor connected in series between the first and the second power lines.

3. The ESD protection circuit as recited in claim 2 , wherein the first inverter is connected between a first node, to which the first resistor and the second capacitor are connected, and the pre-driver.

4. The ESD protection circuit as recited in claim 3 , wherein the first transistor is a PMOS transistor and the second transistor is an NMOS transistor.

5. The ESD protection circuit as recited in any one of claim 4 , wherein the pre-driver is composed of two or more second inverters connected to an output end of the first inverter in a chain shape for buffering and outputting the output signal of the detection unit.

6. The ESD protection circuit as recited in any one of claim 4 , wherein the pre-driver includes:

a second resistor connected to the first power line;

a third transistor, connected between the second resistor and the second power line, which operates in response to an output signal of the first inverter;

a third capacitor connected in parallel to the second resistor between the first power line, and a second node to which the second resistor and the third transistor are connected; and

a second inverter for inverting a voltage at the second node.

7. The ESD protection circuit as recited in claim 6 , wherein a rising time of the power noise is varied at a speed faster than the RC time constant of the RC filter.

8. The ESD protection circuit as recited in claim 7 , wherein the first capacitor has an electrostatic capacity greater than a net parasitic capacity of the first inverter.

9. The ESD protection circuit as recited in claim 8 , wherein the power clamp is composed of a fourth transistor that is connected between the first and the second power lines and operates in response to an output signal of the pre-driver.

10. The ESD protection circuit as recited in claim 9 , wherein the fourth transistor is an NMOS transistor.

11. The ESD protection circuit as recited in claim 9 , wherein the fourth transistor is turned-on to form a current path between the first and the second power lines in order to correspond to an ESD stress current when an ESD stress current having a rising time that is less than the time constant of the RC filter and a duration that is less than or equal to the time constant is flowed into the first and the second power lines, in a state that a power is not applied between the first and the second power lines.

12. The ESD protection circuit as recited in claim 9 , wherein the fourth transistor is kept in a turn-off state to cut off a current path between the first and the second power lines when a power that is ramped-up at a speed slower than the time constant of the RC filter is applied to the first and the second power lines, in a state that a power is not applied between the first and the second power lines.

13. The ESD protection circuit as recited in claim 9 , wherein the fourth transistor is kept in a turn-off state to cut off a current path between the first and the second power lines when a power is applied between the first and the second power lines.

14. The ESD protection circuit as recited in claim 13 , wherein the first capacitor blocks the leakage current caused by the first inverter when the rising time of the power noise varied at a speed faster than the time constant is applied to the first and the second power lines, in a state that a power is applied between the first and the second power lines.

15. The ESD protection circuit as recited in claim 1 , wherein the power clamp is composed of a third transistor that is connected between the first and the second power lines and operates in response to an output signal of the pre-driver.

16. The ESD protection circuit as recited in claim 15 , wherein the third transistor is an NMOS transistor.

17. The ESD protection circuit as recited in claim 15 , wherein the third transistor is turned-on to form a current path between the first and the second power lines in order to correspond to the ESD stress current when an ESD stress current having a rising time that is less than the time constant of the RC filter and duration that is less than or equal to the time constant is flowed into the first and the second power lines, in a state that a power is not applied between the first and the second power lines.

18. The ESD protection circuit as recited in claim 15 , wherein the third transistor is kept in a turn-off state to cut off a current path between the first and the second power lines when a power that is ramped-up at a speed slower than the time constant of the RC filter is applied to the first and the second power lines, in a state that a power is not applied between the first and the second power lines.

19. The ESD protection circuit as recited in claim 15 , wherein the third transistor is kept in a turn-off state to cut off a current path between the first and the second power lines when a power that is ramped-up at a speed slower than the time constant of the RC filter is applied to the first and the second power lines for a predetermined time longer the time constant, in a state that a power is not applied between the first and the second power lines.

20. The ESD protection circuit as recited in claim 15 , wherein the third transistor is kept in a turn-off state to cut off a current path between the first and the second power lines when a power is applied between the first and the second power lines.

21. The ESD protection circuit as recited in claim 20 , wherein the first capacitor blocks the leakage current caused by the first inverter when a rising time of the power noise varied at a speed faster than the time constant is applied to the first and the second power lines, in a state that a power is applied between the first and the second power lines.

22. The ESD protection circuit as recited in claim 15 , wherein the fourth transistor is kept in a turn-off state to cut off a current path between the first and the second power lines when a power that is ramped-up at a speed slower than the time constant of the RC filter is applied to the first and the second power lines for a predetermined time longer than the time constant, in a state that a power is not applied between the first and the second power lines.