IP Library Granted Patent US 7,547,628
Granted Patent B2
US 7,547,628 · App. 11/598,036 · Granted Jun 16, 2009

Method for manufacturing capacitor

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Quick Facts
Patent No.
US 7,547,628
App. No.
11/598,036
Granted
Jun 16, 2009
Kind
B2
Abstract

A method for manufacturing a capacitor includes depositing an interlayer insulating film on or above a plug connected to a switching element, forming a hole in the interlayer insulating film such that the opening portion of the hole is surrounded by an overhang structure and that the plug is exposed in the bottom of the hole, removing the overhang structure, forming a lower electrode on the inner surface of the deep hole, forming a dielectric on the lower electrode, and forming an upper electrode on the dielectric. The above steps prevent the formation of a gap in the capacitor, since the overhang structure as a cause of the gap is removed. The coverage by the dielectric is also prevented from being poor.

Claims (37)

1. A method for manufacturing a semiconductor device, comprising:

depositing an interlayer insulating film on or above a plug connected to a switching element;

forming a hole in said interlayer insulating film such that an opening portion of said hole is surrounded by an overhang structure and that said plug is exposed in a bottom of said hole;

removing said overhang structure;

forming a lower electrode of a capacitor on an inner surface of said hole;

forming a dielectric on said lower electrode; and

forming an upper electrode of the capacitor on said dielectric.

2. The method for manufacturing a semiconductor device, according to claim 1 , wherein said hole is formed to have a bowing shape in which said hole has a maximum hole width, and

wherein said overhang structure is removed such that a hole width of said hole in said opening portion after said removing is greater than said maximum hole width.

3. The method for manufacturing a semiconductor device, according to claim 1 , wherein said depositing said interlayer insulating film comprises:

depositing a first interlayer insulating film on or above said plug; and

depositing a second interlayer insulating film on said first interlayer insulating film,

wherein an etching rate of said second interlayer insulating film is greater than an etching rate of said first interlayer insulating film upon wet etching with a predetermined condition, and

wherein said removing said overhang structure comprises etching said overhang structure by wet etching method with said predetermined condition.

4. The method for manufacturing a semiconductor device, according to claim 1 , wherein said removing said overhang structure comprises:

forming a member in said hole to protect a first portion of a sidewall and not to protect a second portion of said sidewall; and

removing said second portion, wherein said hole is surrounded by said sidewall, and wherein said opening portion is surrounded by said second portion.

5. The method for manufacturing a semiconductor device, according to claim 4 , wherein said member is formed to cover said first portion and not to cover said overhang structure, and

wherein a widest portion of said hole is surrounded by said first portion.

6. The method for manufacturing a semiconductor device, according to claim 4 , wherein said member comprises an organic photoresist film.

7. The method for manufacturing a semiconductor device, according to claim 1 , wherein said forming said hole comprises:

forming a hard mask on said interlayer insulating film;

removing a portion of said hard mask; and forming said hole to have a bowing shape, arranged in said hard mask, in which said hole has a maximum hole width, and

wherein said removing said overhang structure comprises removing said hard mask.

8. The method for manufacturing a semiconductor devices according to claim 1 , wherein said depositing said interlayer insulating film comprises:

depositing a first interlayer insulating film of a first material on or above said plug; and

depositing a second interlayer insulating film of a second material on said first interlayer insulating film,

wherein an etching rate of said second material is greater than an etching rate of said first material upon wet etching with a predetermined condition, and

wherein said removing said overhang structure comprises etching said overhang structure by wet etching method with said predetermined condition.

9. A method of manufacturing a semiconductor device, comprising:

depositing an interlayer insulating film on a semiconductor substrate, said depositing said interlayer insulating film comprising:

depositing a first interlayer insulating film; and

depositing a second interlayer insulating film on said first interlayer insulating film;

forming a hole in said interlayer insulating film such that a top portion of the hole has an inner surface in a shape of an overhang; and

removing said top portion of the hole,

wherein an etching rate of said second interlayer insulating film is greater than an etching rate of said first interlayer insulating film upon wet etching, and

wherein said removing the top portion of the hole comprises removing a top portion of the second interlayer insulating film by the wet etching.

Assignments (9)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 9, 2014
From: ELPIDA MEMORY, INC.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 032645/0422 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 13, 2006
From: IKEDA, NORIAKI
To: ELPIDA MEMORY, INC.
Reel/Frame 018565/0740 →