IP Library Granted Patent US 8,592,866
Granted Patent B2
US 8,592,866 · App. 11/600,102 · Granted Nov 26, 2013

Transistor

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Quick Facts
Patent No.
US 8,592,866
App. No.
11/600,102
Granted
Nov 26, 2013
Kind
B2
Abstract

A transistor includes a first semiconductor layer formed on a substrate, a second semiconductor layer formed on the first semiconductor layer and has a band gap larger than that of the first semiconductor layer, a control layer formed on the second semiconductor layer and contains p-type impurities, a gate electrode formed in contact with at least part of the control layer and a source electrode and a drain electrode formed on both sides of the control layer, respectively. A third semiconductor layer made of material having a lower etch rate than that of the control layer is formed between the control layer and the second semiconductor layer.

Claims (56)

1. A transistor comprising:

a first semiconductor layer formed on a substrate;

a second semiconductor layer formed directly on the first semiconductor layer and has a band gap larger than that of the first semiconductor layer;

a control layer selectively formed on the second semiconductor layer and contains p-type impurities;

a third semiconductor layer formed between the control layer and the second semiconductor layer;

a gate electrode formed on the control layer; and

a source electrode and a drain electrode formed on both sides of the control layer, respectively,

wherein the third semiconductor layer has a band gap larger than that of the second semiconductor layer,

the control layer is apart from the source electrode and the drain electrode,

the source electrode and the drain electrode are in direct contact with the third semiconductor layer,

the first semiconductor layer, the second semiconductor layer and the control layer are made of nitrogen-containing compound semiconductors, respectively,

a length of the control layer is shorter than a length of the third semiconductor layer, a length of the first semiconductor layer and a length of the second semiconductor layer, in a direction perpendicular to a thickness direction,

a thickness of the control layer is larger than a thickness of the second semiconductor layer, and

a thickness of the second semiconductor layer is larger than a thickness of the third semiconductor layer.

2. The transistor of claim 1 , wherein

the control layer is made of AlxGa1−xN (0≦x≦1)

the third semiconductor layer is made of AlyGa1−yN (0≦y≦1 and x<y).

3. The transistor of claim 2 , wherein

the control layer is made of AlxGa1−xN (0≦x≦0.1)

the third semiconductor layer is made of AlyGa1−yN (x+0.1≦y≦1).

4. The transistor of claim 1 , wherein the third semiconductor layer contains p-type impurities.

5. The transistor of claim 4 , wherein the control layer is in contact with the third semiconductor layer.

6. The transistor of claim 5 , wherein the third semiconductor layer is in contact with the second semiconductor layer.

7. The transistor of claim 1 , wherein the third semiconductor layer is made of a compound semiconductor containing at least In.

8. The transistor of claim 1 , further comprising a fourth semiconductor layer formed between the substrate and the first semiconductor layer and has a band gap larger than that of the first semiconductor layer.

9. The transistor of claim 1 , wherein an Al composition ratio is substantially uniform in each of the second semiconductor layer and the third semiconductor layer.

10. The transistor of claim 1 , wherein the third semiconductor layer is a composition gradient layer in which the Al composition ratio gradually decreases in the direction from the second semiconductor layer to the control layer.

11. The transistor of claim 1 , wherein the third semiconductor layer is made of material having a lower etch rate than that of the control layer.

12. The transistor of claim 1 , wherein the third semiconductor layer has a single composition throughout.

13. The transistor of claim 1 , further comprising a passivation film in contact with a side portion of the gate electrode and a side portion of the control layer.

14. The transistor of claim 13 , wherein a thickness of the passivation film is larger than the thickness of the third semiconductor layer.

15. A transistor comprising:

a first semiconductor layer formed on a substrate;

a second semiconductor layer formed directly on the first semiconductor layer and has a band gap larger than that of the first semiconductor layer;

a control layer selectively formed on the second semiconductor layer and contains p-type impurities;

a third semiconductor layer formed between the control layer and the second semiconductor layer;

a gate electrode formed on the control layer; and

a source electrode and a drain electrode formed on both sides of the control layer, respectively, wherein:

the third semiconductor layer is made of material having a lower etch rate than that of the control layer, and has a band gap larger than that of the second semiconductor layer,

the control layer is apart from the source electrode and the drain electrode,

the source electrode and the drain electrode are in contact with the third semiconductor layer,

the first semiconductor layer, the second semiconductor layer and the control layer are made of nitrogen-containing compound semiconductors, respectively, and

the third semiconductor layer is a composition gradient layer in which the Al composition ratio gradually decreases in the direction from the second semiconductor layer to the control layer.

16. A transistor comprising:

a first semiconductor layer formed on a substrate;

a second semiconductor layer formed directly on the first semiconductor layer and has a band gap larger than that of the first semiconductor layer;

a control layer selectively formed on the second semiconductor layer and contains p-type impurities;

a third semiconductor layer formed between the control layer and the second semiconductor layer;

a gate electrode formed on the control layer; and

a source electrode and a drain electrode formed on both sides of the control layer, respectively,

wherein the third semiconductor layer has a band gap larger than that of the second semiconductor layer,

the control layer is apart from the source electrode and the drain electrode,

the source electrode and the drain electrode are in direct contact with the third semiconductor layer,

the first semiconductor layer, the second semiconductor layer and the control layer are made of nitrogen-containing compound semiconductors, respectively,

a thickness of the control layer is larger than a thickness of the second semiconductor layer, and

a thickness of the second semiconductor layer is larger than a thickness of the third semiconductor layer.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 4, 2025
From: INFINEON TECHNOLOGIES AUSTRIA AG
To: PANASONIC HOLDINGS CORPORATION
Reel/Frame 072853/0508 →
CHANGE OF NAME Recorded Dec 13, 2024
From: PANASONIC CORPORATION
To: PANASONIC HOLDINGS CORPORATION
Reel/Frame 069631/0392 →
CHANGE OF NAME Recorded Nov 24, 2008
From: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
To: PANASONIC CORPORATION
Reel/Frame 021897/0689 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 22, 2007
From: YANAGIHARA, MANABU; HIKITA, MASAHIRO; UEDA, TETSUZO; UEMOTO, YASUHIRO; TANAKA, TSUYOSHI
To: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Reel/Frame 019048/0918 →