IP Library Granted Patent US 7,630,693
Granted Patent B2
US 7,630,693 · App. 11/600,351 · Granted Dec 8, 2009

Transmitter with improved power efficiency

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Quick Facts
Patent No.
US 7,630,693
App. No.
11/600,351
Granted
Dec 8, 2009
Kind
B2
Abstract

A power amplifier (PA) line-up ( 210 ) and a method ( 500 ) for more efficiently utilizing battery power are disclosed. PA line-up ( 210 ) includes a driver ( 220 ), a matching circuit ( 214 ), and a PA ( 230 ) coupled to a matching circuit ( 216 ), wherein matching circuit ( 216 ) is configured to be coupled to a filter ( 260 ). PA line-up ( 210 ) includes a transmission line ( 260 ) coupled to matching circuit ( 216 ) and a switch ( 262 ) configured to selectively couple driver ( 220 ) to either matching circuit ( 214 ) or matching circuit ( 216 ) such that signal ( 205 ) is capable of by-passing PA ( 230 ) when signal ( 205 ) does not need to be amplified by PA ( 230 ). Furthermore, PA line-up ( 210 ) may include a second transmission line ( 250 ) so that signal ( 205 ) is capable of by-passing a driver ( 220 ) and a PA ( 230 ) when signal ( 205 ) does not need to be amplified by driver ( 220 ) and PA ( 230 ).

Claims (112)

1. A power amplifier (PA) line-up comprising:

a driver having a driver output;

a PA having a PA input and a PA output;

a first matching circuit having a first matching circuit output coupled to the PA input and having a first matching circuit input, the first matching circuit configured to receive a signal from the driver output and impedance match the signal to the PA input and the driver output;

a second matching circuit having a second matching circuit input coupled to the PA output, a third matching circuit input, and a second matching circuit output configured to be coupled to a filter input, the second matching circuit configured to impedance match the signal to the filter input and at least one of the PA output and the driver output;

a first transmission line coupled to the third matching circuit input; and

a first switch coupled to the driver output, the first switch having a first switch output configured to selectively couple the driver to one of the second matching circuit via the first transmission line and the first matching circuit based upon a pre-determined output power level for the signal.

2. The PA line-up of claim 1 , wherein the second matching circuit comprises a fourth matching circuit input, the PA line-up further comprising:

a pre-driver having a pre-driver output;

a third matching circuit having a third matching circuit output coupled to the driver input and a fifth matching circuit input, the third matching circuit configured to impedance match the signal to the pre-driver output and the driver input;

a second transmission line coupled to the fourth matching circuit input; and

a second switch having a second switch input coupled to the pre-driver output and a second switch output configured to selectively couple the pre-driver to one of the third matching circuit and the second matching circuit via the second transmission line based upon a pre-determined output power level for the signal, wherein the second matching circuit is configured to impedance match the signal to the filter input and at least one of the driver output, the PA output, and the pre-driver output.

3. The PA line-up of claim 2 , further comprising a third switch configured to selectively couple the first transmission line to the third matching circuit input, wherein the third switch is configured to be open when the first switch selectively couples the driver output to the first matching circuit input and configured to be closed when the first switch selectively couples the driver output to the first transmission line.

4. The PA line-up of claim 3 , further comprising a fourth switch configured to selectively couple the second transmission line to the fourth matching circuit input, wherein the fourth switch is configured to be open when the second switch selectively couples the pre-driver output to the fifth matching circuit input and configured to be closed when the fourth switch selectively couples the pre-driver output to the second transmission line.

5. The PA line-up of claim 2 , wherein the second matching circuit is a variable matching circuit.

6. The PA line-up of claim 1 , further comprising a second switch configured to selectively couple the first transmission line to the third matching circuit input, wherein the second switch is configured to be open when the first switch selectively couples the signal generator output to the first matching circuit input and configured to be closed when the first switch selectively couples the signal generator output to the first transmission line.

7. The PA line-up of claim 1 , wherein the second matching circuit is a variable matching circuit.

8. The PA line-up of claim 7 , wherein the second matching circuit further comprises at least one variable capacitor coupled in parallel with at least one inductor.

9. The PA line-up of claim 7 , wherein the second matching circuit further comprises at least one capacitor coupled in parallel with at least one inductor, and a second switch configured to selectively short circuit the at least one capacitor.

10. The PA line-up of claim 7 , wherein the second matching circuit is variable based upon whether the second matching circuit is impedance matching the one of the PA and the driver.

11. The PA line-up of claim 7 , wherein the second matching circuit further comprises:

a first node;

a second node;

a first variable capacitor coupled to the first node and the second node;

a first inductor coupled to the first node and the second node, and coupled in parallel with the first variable capacitor;

a third node coupled to the second node;

a second variable capacitor coupled to the third node and configured to be coupled to ground;

a fourth node coupled to the third node; and

a first capacitor coupled to the fourth node and configured to be coupled to ground.

12. The PA line-up of claim 11 , wherein the second matching circuit further comprises:

a fifth node coupled to the fourth node;

a sixth node;

a third variable capacitor coupled to the fifth node and the sixth node;

a second inductor coupled to the fifth node and the sixth node, and coupled in parallel with the third variable capacitor;

a seventh node coupled to the sixth node;

a fourth variable capacitor coupled to the seventh node and configured to be coupled to ground;

an eighth node coupled to the seventh node; and

a second capacitor coupled to the eighth node and configured to be coupled to ground.

13. The PA line-up of claim 7 , wherein the second matching circuit further comprises:

a first node;

a second node;

a first switch coupled to the first node;

a first capacitor coupled in series with the first switch and coupled to the second node;

a first inductor coupled to the first node and the second node, and coupled in parallel with the first switch and the first capacitor;

a third node coupled to the second node;

a second switch coupled to the third node;

a second capacitor coupled to the second switch and configured to be coupled to ground;

a fourth node coupled to the third node; and

a third capacitor coupled to the fourth node and configured to be coupled to ground.

14. The PA line-up of claim 13 , wherein the second matching circuit further comprises:

a fifth node coupled to the fourth node;

a sixth node;

a third switch coupled to the fifth node;

a fourth capacitor coupled in series with the third switch and coupled to the sixth node;

a second inductor coupled to the fifth node and the sixth node, and coupled in parallel with the third switch and the fourth capacitor;

a seventh node coupled to the sixth node;

a fourth switch coupled to the seventh node;

a fifth capacitor coupled to the fourth switch and configured to be coupled to ground;

an eighth node coupled to the seventh node; and

a sixth capacitor coupled to the eighth node and configured to be coupled to ground.

15. A power amplifier (PA) line-up comprising:

a pre-driver having a pre-driver output;

a driver having a driver input and a driver output;

a first matching circuit having a first matching circuit output coupled to the driver input and having a first matching circuit input, the first matching circuit configured to receive a signal from the pre-driver output and impedance match the signal to the first driver input and the pre-driver output;

a PA having a PA input and a PA output;

a second matching circuit having a second matching circuit input coupled to the driver output and having a second matching circuit output coupled to the PA input, the second matching circuit configured to receive the signal from the driver output and impedance match the signal to the driver output and the PA input;

a third matching circuit having a third matching circuit input coupled to the PA output, a fourth matching circuit input, and a third matching circuit output configured to be coupled to a filter input, the third matching circuit configured to impedance match the signal to the filter input and at least one of the PA output and the pre-driver output;

a transmission line coupled to the fourth matching circuit input; and

a first switch having a first switch input coupled to the pre-driver output, wherein the first switch is configured to selectively couple the pre-driver to one of the third matching circuit via the transmission line and the first matching circuit based upon a pre-determined output power level for the signal.

16. The PA line-up of claim 15 , further comprising a second switch configured to selectively couple the transmission line to the fourth matching circuit input, wherein the second switch is configured to be open when the first switch selectively couples the pre-driver to the first matching circuit and configured to be closed when the first switch selectively couples the pre-driver to the third matching circuit via the transmission line.

17. The PA line-up of claim 15 , wherein the third matching circuit further comprises at least one variable capacitor coupled in parallel with at least one inductor.

18. The PA line-up of claim 15 , wherein the third matching circuit further comprises at least one capacitor coupled in parallel with at least one inductor, and a second switch configured to selectively short circuit the at least one capacitor.

19. The PA line-up of claim 15 , wherein the third matching circuit further comprises:

a first node;

a second node;

a first variable capacitor coupled to the first node and the second node;

a first inductor coupled to the first node and the second node, and coupled in parallel with the first variable capacitor;

a third node coupled to the second node;

a second variable capacitor coupled to the third node and configured to be coupled to ground;

a fourth node coupled to the third node; and

a first capacitor coupled to the fourth node and configured to be coupled to ground.

20. The PA line-up of claim 19 , wherein the third matching circuit further comprises:

a fifth node coupled to the fourth node;

a sixth node;

a third variable capacitor coupled to the fifth node and the sixth node;

a second inductor coupled to the fifth node and the sixth node, and coupled in parallel with the third variable capacitor;

a seventh node coupled to the sixth node;

a fourth variable capacitor coupled to the seventh node and configured to be coupled to ground;

an eighth node coupled to the seventh node; and

a second capacitor coupled to the eighth node and configured to be coupled to ground.

21. The PA line-up of claim 15 , wherein the third matching circuit further comprises:

a first node;

a second node;

a first switch coupled to the first node;

a first capacitor coupled in series with the first switch and coupled to the second node;

a first inductor coupled to the first node and the second node, and coupled in parallel with the first switch and the first capacitor;

a third node coupled to the second node;

a second switch coupled to the third node;

a second capacitor coupled to the second switch and configured to be coupled to ground;

a fourth node coupled to the third node; and

a third capacitor coupled to the fourth node and configured to be coupled to ground.

22. The PA line-up of claim 21 , wherein the third matching circuit further comprises:

a fifth node coupled to the fourth node;

a sixth node;

a third switch coupled to the fifth node;

a fourth capacitor coupled in series with the third switch and coupled to the sixth node;

a second inductor coupled to the fifth node and the sixth node, and coupled in parallel with the third switch and the fourth capacitor;

a seventh node coupled to the sixth node;

a fourth switch coupled to the seventh node;

a fifth capacitor coupled to the fourth switch and configured to be coupled to ground;

an eighth node coupled to the seventh node; and

a sixth capacitor coupled to the eighth node and configured to be coupled to ground.

Assignments (21)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
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CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040632 FRAME: 0001. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Sep 21, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
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CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040632/0001 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
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To: MORGAN STANLEY SENIOR FUNDING, INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
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To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037355/0723 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
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SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SECURITY AGREEMENT Recorded May 13, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
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SECURITY AGREEMENT Recorded Mar 15, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A.
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ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 16, 2006
From: LIU, LIANJUN; USCOLA, RICARDO A.
To: FREESCALE SEMICONDUCTOR, INC.
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