IP Library Granted Patent US 7,598,596
Granted Patent B2
US 7,598,596 · App. 11/602,639 · Granted Oct 6, 2009

Methods and apparatus for a dual-metal magnetic shield structure

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Quick Facts
Patent No.
US 7,598,596
App. No.
11/602,639
Granted
Oct 6, 2009
Kind
B2
Abstract

A shield structure for shielding an electromagnetic-field-susceptible region of a semiconductor component (e.g., a magnetoresistive random access memory, or “MRAM”) includes a stress-relief layer (e.g., electroplated Ni) formed over the semiconductor device in a shield region substantially corresponding to the electromagnetic-field-susceptible region, and a magnetic shield layer (e.g., an electroplated PERMALLOY or MUMETAL layer) mechanically coupled to the stress-relief layer within the shield region, wherein the magnetic shield layer has a stress condition that is substantially opposite of that of the stress-relief layer.

Claims (48)

1. A shield structure for shielding an electromagnetic-field-susceptible region of a semiconductor component located on a substrate that has a top surface and a bottom surface, the structure comprising:

a first shield structure formed over the semiconductor component and the top surface of the substrate, wherein the first shield structure includes

a first stress-relief layer electrodeposited over the semiconductor component in a shield region substantially corresponding to the electromagnetic-field-susceptible region, wherein the first stress-relief layer has a first stress condition, and

a first magnetic shield layer electrodeposited over the stress-relief layer and mechanically coupled to the first stress-relief layer within the shield region, wherein the first magnetic shield layer has a second stress condition that is substantially opposite of the first stress condition, wherein sides of the first stress-relief layer and sides of the first magnetic shield layer define a perimeter of the shield region;

a leadframe; and

a second shield structure formed on the leadframe, wherein the second shield structure includes

a second stress-relief layer formed under the semiconductor component, wherein the second stress-relief layer has the first stress condition, and

a second magnetic shield layer mechanically coupled to the second stress-relief layer, wherein the second magnetic shield layer has the second stress condition, and wherein the bottom surface of the substrate is mounted on the second shield structure.

2. The shield structure of claim 1 , wherein the first stress condition is tensile, and the second stress condition is compressive.

3. The shield structure of claim 1 , wherein the first stress-relief layer comprises a Ni layer.

4. The shield structure of claim 3 , wherein the first stress-relief layer comprises an electroplated Ni layer.

5. The shield structure of claim 1 , wherein the first magnetic shield layer comprises a NiFe alloy.

6. The shield structure of claim 5 , wherein the first magnetic shield layer comprises an NiFe alloy.

7. The shield structure of claim 6 , wherein the first magnetic shield layer has a composition consisting of approximately 80% Ni and 20% Fe.

8. The shield structure of claim 1 , wherein the electromagnetic-field-susceptible region has a perimeter that is entirely encompassed by the shield region.

9. A method of forming a shield structure for shielding an electromagnetic-field-susceptible region of a semiconductor component located on a substrate that has a top surface and a bottom surface, the method comprising:

forming a first shield structure over the semiconductor component and the top surface of the substrate, by

electrodepositing a first stress-relief layer over the semiconductor component within an opening in a photoresist layer, wherein the opening defines a shield region that substantially corresponds to the electromagnetic-field-susceptible region of the semiconductor device, and the first stress-relief layer has a first stress condition, and

electrodepositing a first magnetic shield layer over the first stress-relief layer within the opening, wherein the first magnetic shield layer has a second stress condition that is substantially opposite of the first stress condition;

forming a second shield structure on a leadframe by

forming a second stress-relief layer on the leadframe, wherein the second stress-relief layer has the first stress condition, and

forming a second magnetic shield layer mechanically coupled to the second stress-relief layer, wherein the second magnetic shield layer has the second stress condition; and

coupling the second shield structure to the bottom surface of the substrate.

10. The method of claim 9 , wherein electrodepositing the first stress-relief layer comprises depositing a Ni layer.

11. The method of claim 9 , wherein electrodepositing the first magnetic shield layer comprises electrodepositing a NiFe alloy.

12. The method of claim 11 , wherein electrodepositing the first magnetic shield layer comprises electrodepositing a layer comprising approximately 80% Ni and 20% Fe.

13. The method of claim 9 , wherein electrodepositing the first magnetic shield layer includes electrodepositing the first magnetic shield layer such that the electromagnetic-field-susceptible region has a perimeter that is entirely encompassed by the shield region.

14. The method of claim 9 , further including forming a polymer layer over the semiconductor component prior to the electrodepositing of the first stress-relief layer.

15. The method of claim 14 , further including forming a seed layer over the polymer layer prior to the electrodepositing of the first stress-relief layer, wherein the seed layer provides a starting point for the first stress-relief layer.

16. A magnetoresistive random access memory (MRAM) component comprising:

a ferromagnetic memory cell on a substrate having a top surface and a bottom surface;

a first shield structure formed over the ferromagnetic memory cell on the top surface of the substrate, wherein the first shield structure includes

a first stress-relief layer electrodeposited over the ferromagnetic memory cell, wherein the first stress-relief layer has a first stress condition, and

a first magnetic shield layer electrodeposited over the stress-relief layer, wherein the first magnetic shield layer has a second stress condition that is substantially opposite of the first stress condition, and wherein sides of the stress-relief layer and sides of the magnetic shield layer define a perimeter of a shield region;

a leadframe coupled with the bottom surface of the substrate; and

a second shield structure formed on the leadframe, wherein the second shield structure includes

a second stress-relief layer, which has the first stress condition, and

a second magnetic shield layer mechanically coupled to the second stress-relief layer, wherein the second magnetic shield layer has the second stress condition.

17. The MRAM component of claim 16 , wherein the first stress-relief layer comprises an electrodeposited Ni layer, and the first magnetic shield layer comprises an electrodeposited layer comprising approximately 80% Ni and 20% Fe.

18. The MRAM component of claim 16 , wherein the MRAM component further includes a non-conductive polymeric layer over the ferromagnetic memory cell, and a seed layer over the polymeric layer.

19. A shield structure for shielding an electromagnetic-field-susceptible region of a semiconductor component that is located on a substrate that has a top surface and a bottom surface, the structure comprising:

a first shield structure formed over the semiconductor component and the top surface of the substrate, wherein the first shield structure includes

a first stress-relief layer formed over the semiconductor component in a shield region substantially corresponding to the electromagnetic-field-susceptible region, wherein the first stress-relief layer has a first stress condition, and

a first magnetic shield layer mechanically coupled to the first stress-relief layer within the shield region, wherein the first magnetic shield layer has a second stress condition that is substantially opposite of the first stress condition, wherein sides of the first stress-relief layer and sides of the first magnetic shield layer define a perimeter of the shield region;

a leadframe; and

a second shield structure formed on the leadframe, wherein the second shield structure includes

a second stress-relief layer, which has the first stress condition, and

a second magnetic shield layer mechanically coupled to the second stress-relief layer, wherein the second magnetic shield layer has the second stress condition, and wherein the second shield structure is coupled with the bottom surface of the substrate.

Assignments (17)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
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CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040632 FRAME: 0001. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Sep 21, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
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CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040632/0001 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
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To: MORGAN STANLEY SENIOR FUNDING, INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
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To: MORGAN STANLEY SENIOR FUNDING, INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0143 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037355/0723 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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