Semiconductor device having trench-gate transistor with parallel channel regions in gate trench
View Patent ↗A semiconductor device includes, on a semiconductor substrate, an active region surrounded by an STI region, a gate trench formed in one direction transverse to the active region, a gate insulating film formed on a side surface of the gate trench, an insulating film formed on a bottom of the gate trench and thicker than the gate insulating film, and a gate electrode having at least a part of the gate electrode formed in the gate trench. Portions of the semiconductor substrate present in the active region and located on both sides of the gate trench in an extension direction of the gate trench function as a source region and a drain region, respectively. A portion of the semiconductor substrate located between the side surface of the active region (the side of the STI region) and the side surface of the gate trench functions as a channel region.
1. A semiconductor device, comprising:
an STI (Shallow Trench Isolation) region formed on a semiconductor substrate;
an active region surrounded by the STI region;
a gate trench formed in a predetermined direction to cross the active region;
a gate insulating film formed on a side surface of the gate trench;
an insulating film that is formed on a bottom of the gate trench and is thicker than the gate insulating film; and
a gate electrode, at least a part of which is formed in the gate trench,
wherein said semiconductor substrate present in the active region includes a first portion located on both sides of the gate trench with respect to the predetermined direction and a second portion located between a side surface of the STI region and the side surface of the gate trench,
wherein said first portion of the semiconductor substrate functions as a source region and a drain region, and said second portion of the semiconductor substrate functions as a channel region, and
wherein the insulating film formed on the bottom of the gate trench is set to have a thickness within a degree such that no channel is formed in the semiconductor substrate located on the bottom of the gate trench.
2. A semiconductor device, comprising:
a semiconductor body of a first conductivity type;
a channel region of the first conductivity type projecting from a part of the semiconductor body with an upwardly tapered shape, the channel region thereby including a first side surface which is inclined with respect to an upper surface of the semiconductor body, a second side which is opposite to the first side surface, a third side interface which interfaces between respective one ends of the first and second side surfaces, and a fourth side interface which is opposite to the third side interface to interface between respective other ends of the first and second side surfaces;
an isolation region formed in contact with the first side surface of the channel region;
a gate structure formed in contact with the second side surface of the channel region, the gate structure including a gate electrode and a gate insulating film intervening between the gate electrode and the second side surface of the channel region; and
source and drain regions formed in contact respectively with the third and fourth side interfaces of the channel region, each of the source and drain regions being of a second conductivity type.
3. The device as claimed in claim 2 , further comprising:
an additional channel region of the first conductivity type projecting from another part of the semiconductor body with an upwardly tapered shape, the additional channel region thereby including a fifth side surface which is inclined with respect to the upper surface of the semiconductor body, a sixth side surface which is opposite to the fifth side surface, a seventh side interface which interfaces between respective one ends of the fifth and sixth side surfaces, and an eighth side interface which is opposite to the seventh side interface to interface between respective other ends of the fifth and sixth side surfaces,
wherein the isolation region being further in contact with the fifth side surface of the channel region, the gate structure being further in contact with the sixth side surface of the channel region with an intervention of the gate insulating film between the gate electrode and the sixth side surface of the channel region, and the source and drain regions being further in contact respectively with the seventh and eighth side interfaces of the additional channel region.
4. The device as claimed in claim 3 , wherein each of the second and sixth side surfaces of the channel regions is oblique with respect to the upper surface of the semiconductor body so that an upper portion of each of the channel region and the additional channel region is smaller than the bottom of each of the channel region and the additional channel region.
5. The device as claimed in claim 3 , further comprising an insulating layer formed between the gate electrode and a portion of the semiconductor body between the channel region and the additional channel region, the insulating layer being greater in thickness than the gate insulating film.
6. The device as claim in claim 2 , wherein the second side surface of the channel region is oblique with respect to the upper surface of the semiconductor body so that an upper portion of the channel region is smaller than a bottom portion of the channel region.
7. The device as claimed in claim 2 , wherein the isolation region comprises an insulating material.
8. The device as claimed in claim 2 , further comprising an insulating layer formed between the gate electrode and the semiconductor body, the insulating layer being greater in thickness than the gate insulating film.
9. The device as claimed in claim 2 , wherein the gate electrode comprises a semiconductor layer and metal layer stacked on the semiconductor layer.