Three-dimensional integrated circuit structure
View Patent ↗A semiconductor structure includes an interconnect region and a semiconductor stack bonded to the interconnect region through a bonding region. The stack includes at least two semiconductor layers having different electrical properties. The stack also includes single crystalline semiconductor material. The stack can be processed to form a mesa structure and the mesa structure can be processed to from a vertically oriented semiconductor device.
1. An apparatus, comprising:
a substrate which carries an electronic circuit and an interconnect region; and
a vertically oriented semiconductor device bonded to the interconnect region through a bonding region, the semiconductor device including a mesa structure having a pn junction.
2. The apparatus of claim 1 , wherein the bonding region includes a metal layer.
3. The apparatus of claim 1 , wherein opposed surfaces of the mesa structure include planarized surfaces.
4. The apparatus of claim 1 , wherein the interconnect region includes a conductive line, the electronic circuit and vertically oriented semiconductor device being in communication with each other through the conductive line.
5. The apparatus of claim 1 , wherein the vertically oriented semiconductor device is operated in response to a signal provided by the electronic circuit.
6. The apparatus of claim 1 , wherein the mesa structure includes crystalline semiconductor material.
7. The apparatus of claim 1 , wherein the vertically oriented semiconductor device includes a control terminal which adjusts the conductivity of the mesa structure in response to a signal from the electronic circuit.
8. An apparatus, comprising:
a substrate which carries an electronic circuit and interconnect region; and
a vertically oriented semiconductor device bonded to the interconnect region through a bonding region, the semiconductor device including a mesa structure having a pn junction and opposed planarized surfaces, wherein the pn junction extends between the opposed planarized surfaces.
9. The apparatus of claim 8 , wherein the bonding region includes a metal material.
10. The apparatus of claim 9 , wherein the vertically oriented semiconductor device is bonded to the interconnect region through a bonding interface established by the bonding region.
11. The apparatus of claim 10 , wherein the bonding interface is not a growth interface.
12. The apparatus of claim 8 , wherein the bonding region includes first and second conductive bonding layers with a bonding interface extending therebetween, wherein the electronic circuit is in communication with the vertically oriented semiconductor device through the interconnect region and first and second conductive bonding layers.