Circuit for generating data strobe signal of semiconductor memory device

1. A circuit for generating a data strobe signal of a semiconductor memory device, comprising:

a first internal clock delay unit for delaying an internal clock signal according to a first operating frequency;

a second internal clock delay unit for delaying an internal clock signal according to a second operating frequency;

a selecting control unit for selecting one of an output signals from the first internal clock delay unit and the second internal clock delay unit; and

a data strobe signal generating unit for generating a data strobe signal in response to a data latch control signal and an output signal from the selecting control unit.

2. The circuit according to claim 1 , wherein the first internal clock delay unite is configured to adjust a tDQSS characteristic to the first operating frequency; and

wherein the second internal clock delay unit is configured to adjust a tDQSS characteristic according to the second operating frequency.

3. The circuit according to claim 1 , wherein the first internal clock delay unite comprises:

a first logic operation unit for performing a logic operation on the internal clock signal and a first control signal, wherein the first control signal has an information of the first operation frequency; and

a first delay unit for delaying an output signal from the first logic operation unit; and

wherein the second internal clock delay unit comprises:

a second logic operation unit for performing a logic operation on the internal clock signal and a second control signal, wherein the second control signal has an information of the second operation frequency; and

a second delay unit for delaying an output signal from the second logic operation unit.

4. The circuit according to claim 3 , wherein the logic operation unit includes a NAND gate.

5. The circuit according to claim 1 , wherein the selecting control unit comprises a first transmission gate and a second transmission gate,

wherein the first transmission gate for selectively outputting an output signal from the first internal clock delay unit; and

wherein the second transmission gate for selectively outputting an output signal from the second internal clock delay unit.

6. A circuit for generating a data strobe signal of a semiconductor memory device, comprising:

a plurality of internal clock delay units for delaying an internal clock signal in response to a plurality of combination signals, respectively;

a selecting control unit for selecting one of output signals from the plurality of internal clock delay units;

a data strobe signal generating unit for generating a data strobe signal in response to a data latch control signal and an output signal from the selecting control unit; and

a plurality of combination units for combining a plurality of control signals to output the plurality of signals, respectively;

wherein the plurality of control signals each has an information of corresponding to an operation frequency.

7. The circuit according to claim 6 , wherein each of the plurality of internal clock delay units is configured to adjust a tDQSS characteristic corresponding to each tCK at a different delay timing in response to the plurality of combination signals, respectively.

8. The circuit according to claim 6 , wherein each of the plurality of combination units comprises a logic operation unit for performing a logic operation on the plurality of corresponding to control signals.

9. The circuit according to claim 8 , wherein the logic operation unit includes a NOR gate.

10. The circuit according to claim 6 , wherein each of the plurality of internal clock delay units comprises:

a logic operation unit for performing a logic operation on the internal clock signal and one of the plurality of combination signals;

a delay unit for delaying an output signal from the logic operation unit.

11. The circuit according to claim 10 , wherein the logic operation unit includes a NAND gate.

12. The circuit according to claim 6 , wherein the selecting control unit comprises a plurality of transmission gate for selectively outputting output signals from the plurality of internal clock delay units.

13. The circuit according to claim 1 , wherein the selecting control unit selects one of an output signals from the first internal clock delay unit and the second internal clock delay unit according to the first operation frequency and the second operation frequency.

14. The circuit according to claim 1 , wherein the data strobe signal generating unit comprises;

a logic operation unit for performing a logic operation on the data latch control signal and the output signal from the selecting control unit; and

a pulse generating unit for generating the data strobe signal having a predetermined pulse width in response to an output signal from the logic operation unit.

15. The circuit according to claim 8 , wherein the selecting control unit selects one of an output signals from the plurality of internal clock delay units in response to the plurality of combination signals.

16. The circuit according to claim 6 , wherein the data strobe signal generating unit comprises;

a logic operation unit for performing a logic operation on the data latch control signal and the output signal from the selecting control unit; and

a pulse generating unit for generating the data strobe signal having a predetermined pulse width in response to an output signal from the logic operation unit.