IP Library Granted Patent US 7,691,668
Granted Patent B2
US 7,691,668 · App. 11/612,992 · Granted Apr 6, 2010

Method and apparatus for multi-chip packaging

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Quick Facts
Patent No.
US 7,691,668
App. No.
11/612,992
Filed
Dec 19, 2006
Granted
Apr 6, 2010
Kind
B2
Art Unit
2813
USPC
438/106
Abstract

A method and apparatus are provided for multi-chip packaging. A multi-chip package ( 100 ) includes a substrate ( 105 ) and a plurality of semiconductor dice ( 110, 120, 130 ). A first semiconductor die ( 110 ) is physically coupled to an upper face of the substrate ( 105 ), the first semiconductor die ( 110 ) being a smallest one of the plurality of semiconductor dice ( 110, 120, 130 ).

Claims (20)

1. A method for packaging a plurality of semiconductor dice into a single package comprising the steps of:

providing a substrate;

coupling a first one of the plurality of semiconductor dice to the substrate, wherein the first one of the plurality of semiconductor dice is smaller than all other ones of the plurality of semiconductor dice; and

coupling a second one of the plurality of semiconductor dice to the substrate via a first spacer, wherein the first spacer is adhered to an upper face of the first one of the plurality of semiconductor dice and has a perimeter of a lower face that is smaller than a perimeter of the upper face of the first one of the plurality of semiconductor dice, and

wherein the second one of the plurality of semiconductor dice is larger than the first one of the plurality of semiconductor dice and the first and second ones of the plurality of semiconductor dice are smaller than all other ones of the plurality of semiconductor dice.

2. The method in accordance with claim 1 wherein the step of providing the substrate comprises the steps of:

forming an electrically conductive layer in a predefined pattern on an upper face of the substrate; and

providing the substrate with the electrically conductive layer formed thereon for assembly, and

wherein the step of coupling the first one of the plurality of semiconductor dice to the substrate comprises the step of physically coupling a lower face of the first one of the plurality of semiconductor dice to the upper face of the substrate.

3. The method in accordance with claim 2 wherein the step of coupling the first one of the plurality of semiconductor dice to the substrate further comprises the step of electrically coupling the first one of the plurality of semiconductor dice to a first portion of the electrically conductive layer of the substrate.

4. The method in accordance with claim 1 wherein the plurality of semiconductor dice is three or more semiconductor dice, and wherein the step of physically coupling the second one of the plurality of semiconductor dice to the first one of the plurality of semiconductor dice further comprises the step of physically coupling a lower face of the second one of the plurality of semiconductor dice to an upper face of the first spacer.

5. The method in accordance with claim 4 further comprising, after the step of physically coupling the second one of the plurality of semiconductor dice to the first one of the plurality of semiconductor dice, the step of electrically coupling the second one of the plurality of semiconductor dice to a second portion of the electrically conductive layer of the substrate.

6. The method in accordance with claim 5 wherein the second one of the plurality of semiconductor dice includes one or more external contacts on an upper face thereof, and wherein the second portion of the electrically conductive layer of the substrate comprises a plurality of contact pads, and wherein the step of electrically coupling the second one of the plurality of semiconductor dice to the second portion of the electrically conductive layer of the substrate comprises the step of wirebonding the one or more external contacts of the second one of the plurality of semiconductor dice to one or more of the plurality of contact pads of the second portion of the electrically conductive layer of the substrate.

7. The method in accordance with claim 6 wherein the electrically conductive layer of the substrate comprises a plurality of contact pads comprising a first portion of the plurality of contact pads, a second portion of the plurality of contact pads and a third portion of the plurality of contact pads, and wherein the each of the plurality of semiconductor dice has contact pads formed on an upper face thereof, and wherein the step of coupling a first one of the plurality of semiconductor dice to the substrate comprises the step of electrically coupling the first one of the plurality of semiconductor dice to a first portion of the plurality of contact pads, the method further comprising the steps of:

after the step of physically coupling the second one of the plurality of semiconductor dice to the first one of the plurality of semiconductor dice, electrically coupling the second one of the plurality of semiconductor dice to the second portion of the plurality of contact pads;

physically coupling a third one of the plurality of semiconductor dice to the second one of the plurality of semiconductor dice, the third one of the plurality of semiconductor dice being larger than the first and second ones of the plurality of semiconductor dice; and

electrically coupling the third one of the plurality of semiconductor dice to the third portion of the plurality of contact pads.

8. The method in accordance with claim 7 wherein the step of physically coupling the third one of the plurality of semiconductor dice to the second one of the plurality of semiconductor dice comprises the steps of:

adhering a second spacer to an upper face of the second one of the plurality of semiconductor dice, the second spacer having a perimeter of a lower face thereof smaller than a perimeter of the upper face of the second one of the plurality of semiconductor dice; and

physically coupling a lower face of the third one of the plurality of semiconductor dice to an upper face of the second spacer.

Assignments (8)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 15, 2022
From: CYPRESS SEMICONDUCTOR CORPORATION
To: INFINEON TECHNOLOGIES LLC
Reel/Frame 059721/0467 →
RELEASE OF SECURITY INTEREST Recorded Mar 16, 2022
From: MUFG UNION BANK, N.A.
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 059410/0438 →
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Oct 28, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MUFG UNION BANK, N.A.
Reel/Frame 050896/0366 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 1, 2015
From: SPANSION, LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 036043/0013 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
RELEASE OF SECURITY INTEREST Recorded Mar 13, 2015
From: BARCLAYS BANK PLC
To: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY LLC
Reel/Frame 035201/0159 →
SECURITY AGREEMENT Recorded Jun 4, 2010
From: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY INC.; SPANSION TECHNOLOGY LLC
To: BARCLAYS BANK PLC
Reel/Frame 024522/0338 →