Granted Patent B2

US 7,626,882 · App. 11/613,383 · Granted Dec 1, 2009

Abstract

Claims (43)

1. A method for performing a high voltage operation in a semiconductor memory device selectably connectable to an external high voltage power supply providing a high voltage signal thereto, the method comprising the steps of:

detecting a power-on period of an operational voltage signal provided to the semiconductor memory device;

waiting a time delay interval after detection of the power-on period of the operational voltage, the time delay interval determined in response to the high voltage signal; and

connecting the high voltage signal and the operational voltage signal to memory cells of the semiconductor memory device for performing memory operations thereof.

2. The method of claim 1 wherein the step of waiting a time delay interval comprises the step of waiting a predetermined time delay interval determined in response to a value stored in a storage portion of the semiconductor memory device.

3. The method of claim 2 wherein the predetermined time delay interval is between fifty microseconds and four hundred microseconds.

4. The method of claim 3 wherein the predetermined time delay interval is approximately two hundred microseconds.

5. The method of claim 2 further comprising the step of one time programmably storing the value in the storage portion of the semiconductor memory device.

6. The method of claim 1 wherein the semiconductor memory device further includes an internal high voltage power supply, and wherein the step of activating the external high voltage power supply comprises the steps of:

determining whether to supply the high voltage signal for high voltage memory operations in the memory cells from the external high voltage power supply or the internal high voltage power supply; and

connecting the external high voltage power supply to the memory cells to provide the high voltage signal thereto in response to determining to supply the high voltage signal for the high voltage memory operations from the external high voltage power supply.

7. The method of claim 1 wherein the step of waiting a time delay interval comprises the steps of:

monitoring the high voltage signal to detect stabilization of the high voltage signal; and

determining an end of the time delay interval in response to detection of stabilization of the high voltage signal.

8. The method of claim 7 wherein the semiconductor memory device includes a stable high voltage signal detector, and wherein the step of monitoring the high voltage signal comprises the step of the stable high voltage signal detector monitoring the high voltage signal, and wherein the step of determining the end of the time delay interval comprises the step of generating a stable voltage signal in response to detection of stabilization of the high voltage signal, and wherein the step of connecting the high voltage signal to the memory cells comprises the step of connecting the high voltage signal to the memory cells for performing the memory operations thereof in response to the stable voltage signal.

9. A semiconductor memory device selectably connectable to an external high voltage power supply, the semiconductor memory device comprising:

a switch connected to external voltage supply signals for selectably coupling the external voltage supply signals to memory cells of the semiconductor memory device for memory operations thereof, the external voltage supply signals including a high voltage signal provided from the external high voltage power supply and an operational voltage signal;

a detector connected to the external voltage supply signals for generating a timer activation signal in response to detecting an operational voltage power-on period; and

a timing device coupled to the detector and the switch for signaling the switch to decouple the high voltage signal and the operational voltage signal from the memory cells in response to the timer activation signal and to recouple the high voltage signal and the operational voltage signal to the memory cells a time delay interval thereafter, the time delay interval determined in response to the high voltage signal.

10. The semiconductor memory device of claim 9 wherein the time delay interval is a predetermined time delay interval, and wherein the timing device includes a timer for measuring the predetermined time delay interval in response detection of the operational voltage power-on period, the timer signaling the switch to recouple the high voltage signal and the operational voltage signal to the memory cells after the predetermined time delay interval is measured.

11. The semiconductor memory device of claim 10 further comprising a storage portion storing a value representing the predetermined time delay interval, wherein the timer is coupled to the storage portion and retrieves the value from the storage portion and measures the predetermined time delay interval in response to the value retrieved.

12. The semiconductor memory device of claim 11 wherein the predetermined time delay interval is between fifty microseconds and four hundred microseconds.

13. The semiconductor memory device of claim 12 wherein the predetermined time delay interval is approximately two hundred microseconds.

14. The semiconductor memory device of claim 9 further comprising:

a memory controller coupled to the switch and the memory cells and controlling at least a portion of memory operations of the memory cells; and

an internal high voltage power supply coupled to the memory controller, wherein the memory controller determines whether to supply the high voltage signal to the memory cells for the high voltage operations thereof from the external high voltage power supply or the internal high voltage power supply and signals the switch to connect the external high voltage power supply to the memory cells in response to determining to supply the high voltage signal for the high voltage operations from the external high voltage power supply.

15. The semiconductor memory device of claim 9 wherein the timing device monitors the high voltage signal to detect stabilization thereof and determines an end of the time delay interval in response to detection of stabilization of the high voltage signal.

16. The semiconductor memory device of claim 15 wherein the timing device includes a stable high voltage signal detector coupled to the high voltage power supply and generating a stable voltage signal in response to detection of stabilization of the high voltage signal, and wherein the stable high voltage signal detector provides the stable voltage signal to the switch to recouple the high voltage signal and the operational voltage signal to the memory cells for performing the memory operations thereof in response to the stable voltage signal.

17. A semiconductor package comprising:

a semiconductor memory die including memory cells and connected to an operational voltage signal; and

a high voltage power supply semiconductor die connected to the operational voltage signal for generating a high voltage signal, the high voltage power supply semiconductor die coupled to the semiconductor memory die to provide a high voltage signal to the semiconductor memory die for memory operations thereof, wherein the semiconductor memory die includes:

a switch coupled to the high voltage power supply semiconductor die and the operational voltage signal to selectably provide the high voltage signal and the operational voltage signal to the memory cells for the memory operations thereof;

a detector connected to the external voltage supply signals for generating a timer activation signal in response to detecting an operational voltage power-on period; and

a timing device coupled to the detector and the switch for signaling the switch to decouple the high voltage signal and the operational voltage signal from the memory cells in response to the timer activation signal and for recoupling the high voltage signal and the operational voltage signal to the memory cells a time delay interval thereafter, the time delay interval determined in response to the high voltage signal.

18. An electronic device comprising:

a controller for controlling operations of the electronic device;

a memory coupled to the controller for storing information therein for utilization by the controller for controlling the operations of the electronic device; and

a high voltage power supply external to the memory and providing a high voltage signal to the memory for high voltage memory operations thereof, wherein the memory includes:

a switch coupled to the high voltage power supply semiconductor die and the operational voltage signal to selectably provide the high voltage signal and the operational voltage signal to the memory cells for the memory operations thereof; and

a detector connected to the external voltage supply signals for generating a timer activation signal in response to detecting an operational voltage power-on period; and

a timing device coupled to the detector and the switch for signaling the switch to decouple the high voltage signal and the operational voltage signal from the memory cells in response to the timer activation signal and for recoupling the high voltage signal and the operational voltage signal to the memory cells a time delay interval thereafter, the time delay interval determined in response to the high voltage signal.

19. The electronic device of claim 18 wherein the time delay interval is a predetermined time delay interval and wherein the memory further includes a storage portion storing a value representing the predetermined time delay interval, and wherein the timing device includes a timer for measuring the predetermined time delay interval in response detection of the operational voltage power-on period, the timer signaling the switch to recouple the high voltage signal and the operational voltage signal to the memory cells after the predetermined time delay interval is measured.

20. The electronic device of claim 18 wherein the timing device includes a stable high voltage signal detector coupled to the high voltage power supply and generating a stable voltage signal in response to detection of stabilization of the high voltage signal, and wherein the stable high voltage signal detector provides the stable voltage signal to the switch to recouple the high voltage signal and the operational voltage signal to the memory cells for performing the memory operations thereof in response to the stable voltage signal.

Assignments (8)