Zero interface polysilicon to polysilicon gate for flash memory
View Patent ↗A system and method are disclosed for processing a zero angstrom oxide interface dual poly gate structure for a flash memory device. An exemplary method can include removing an oxide on a surface of a first poly layer and forming a second poly layer on the first poly layer in a same processing chamber. A transfer of the structure is not needed from an oxide removal tool to, for example, a poly layer formation tool, an implant tool, and the like. As a result, impurities containing a silicon oxide caused by exposure of the first poly layer to an oxygen-containing atmosphere do not form at the interface of the first and second poly layers.
1. A method for forming a zero angstrom oxide interface dual poly gate structure for a flash memory device comprising a core region and a periphery region on a substrate, the method comprising:
forming a dielectric layer over the substrate only in the periphery region;
forming a first poly layer over the dielectric layer only in the periphery region;
contacting the first poly layer with an oxide removing ambient that consists of at least 20% nitrogen and remaining gases selected from a group consisting of helium, neon, argon, krypton, xenon, and combinations thereof at a temperature of 500 degrees Celsius or more and 850 degrees Celsius or less, at a pressure of about 6 Torr or less, and for about 10 seconds or more and about 5 minutes or less to remove an oxide and/or oxide layer on the first poly layer in the processing chamber; and
forming a second poly layer over the first poly layer in the processing chamber,
wherein an interface of the first poly layer and the second poly layer comprises substantially no oxide.
2. The method of claim 1 , further comprising:
forming a portion of a silicon oxide layer in the first poly layer.
3. The method of claim 1 , further comprising:
forming a patterned photoresist over the first poly layer; and
implanting oxygen in the first poly layer.
4. The method of claim 1 , wherein the dielectric layer is formed over the substrate so that the upper surface of the substrate is in contact with the bottom surface of the dielectric layer, and the first poly layer is formed over the dielectric layer so that the upper surface of the dielectric layer is in contact with the bottom surface of the first poly layer.