MEMORY SYSTEM WITH SELECT GATE ERASE
A memory system includes a substrate, forming a first insulator over the substrate, forming a charge trap layer, having a composition for setting a predetermined electrical charge level, over the first insulator, and forming a second insulator over the charge trap layer.
1 . A memory system comprising:
providing a substrate;
forming a first insulator over the substrate;
forming a charge trap layer, having a composition for setting a predetermined electrical charge level, over the first insulator; and
forming a second insulator over the charge trap layer.
2 . The system as claimed in claim 1 further comprising forming a gate layer over the second insulator.
3 . The system as claimed in claim 1 further comprising forming a spacer adjacent to the charge trap layer, and the second insulator.
4 . The system as claimed in claim 1 further comprising applying radiation on the charge trap layer.
5 . The system as claimed in claim 1 wherein forming the charge trap layer includes forming a nitride layer.
6 . A memory system comprising:
providing a semiconductor substrate;
forming a first insulator over a semiconductor substrate;
forming a charge trap layer, having a composition for tuning a predetermined electrical trigger level, over the first insulator;
forming a second insulator isolating the charge trap layer on a side opposite the first insulator; and
applying a radiation source over the first insulator, the charge trap layer, and the second insulator.
7 . The system as claimed in claim 6 further comprising forming a polysilicon gate electrode over the second insulator.
8 . The system as claimed in claim 6 further comprising forming a nitride spacer adjacent to the charge trap layer, and the second insulator.
9 . The system as claimed in claim 6 wherein applying the radiation source includes applying an ultraviolet light source.
10 . The system as claimed in claim 6 wherein forming the charge trap layer includes forming a silicon nitride layer.
11 . A memory system comprising:
a substrate;
a first insulator over the substrate;
a charge trap layer, having a composition for setting a predetermined electrical charge level, over the first insulator; and
a second insulator over the charge trap layer.
12 . The system as claimed in claim 11 further comprising a gate layer over the second insulator.
13 . The system as claimed in claim 11 further comprising a spacer adjacent to the charge trap layer, and the second insulator.
14 . The system as claimed in claim 11 further comprising radiation on the charge trap layer.
15 . The system as claimed in claim 11 wherein the charge trap layer is a nitride layer.
16 . The system as claimed in claim 11 wherein:
the substrate is a semiconductor substrate;
the first insulator layer is over a semiconductor substrate;
the charge trap layer has a composition for tuning a predetermined electrical trigger level;
the second insulator isolates the charge-storage layer on a side opposite the first insulator; and further comprising:
a radiation source over the first insulator, the charge trap layer and the second insulator.
17 . The system as claimed in claim 16 further comprising a polysilicon gate electrode over the second insulator.
18 . The system as claimed in claim 16 further comprising a nitride spacer adjacent to the charge trap layer, and the second insulator.
19 . The system as claimed in claim 16 wherein the radiation source includes an ultraviolet light source.
20 . The system as claimed in claim 16 wherein the charge trap layer includes a silicon nitride layer.