Granted Patent B2

US 7,879,718 · App. 11/616,544 · Granted Feb 1, 2011

Abstract

Claims (60)

1. A method for forming an interconnect in a semiconductor memory device, the method comprising:

forming a pair of source select transistors on a substrate, where forming each of the pair of source select transistors comprises:

forming a first dielectric layer on the substrate,

forming a charge storage layer on the first dielectric layer,

forming a second dielectric layer on the charge storage layer, and

forming a control gate layer on the second dielectric layer;

forming a source region in the substrate between the pair of source select transistors;

forming a first inter-layer dielectric between the pair of source select transistors;

depositing a mask layer over the pair of source select transistors and the first inter-layer dielectric,

where the mask layer defines a local interconnect area between the pair of source select transistors having a width less than a distance between the pair of source select transistors;

etching the semiconductor memory device to remove a portion of the first inter-layer dielectric in the local interconnect area, thereby exposing the source region; and

forming a metal contact in the local interconnect area.

2. The method of claim 1 , where the width of the local interconnect area is between 40 nm and 60 nm less than a distance between the pair of source select transistors.

3. The method of claim 1 , where the control gate layer is a polysilicon layer having a thickness ranging from about 1000 Å to about 2000 Å.

4. The method of claim 1 , where the charge storage layer is a silicon nitride layer having a thickness ranging from about 25 Å to about 500 Å.

5. The method of claim 4 , where the silicon nitride layer is configured to store more than one bit of information therein.

6. The method of claim 1 , further comprising: forming a gate silicide region in the control gate layer of each source select transistors.

7. The method of claim 1 , further comprising: forming a source silicide region in the source region.

8. The method of claim 1 , further comprising, prior to forming the first inter-layer dielectric:

forming a dielectric liner layer over the substrate and the pair of source select transistors; and

forming a spacer layer over the dielectric liner layer,

where the spacer layer is etched to expose at least a portion of the dielectric liner layer over the source region.

9. The method of claim 8 , further comprising forming a dielectric etch stop layer over the spacer layer and the dielectric liner layer prior to forming the first inter-layer dielectric.

10. The method of claim 9 , where the dielectric etch stop layer is a silicon nitride layer having a thickness ranging from about 100 Å to about 1000 Å.

11. The method of claim 9 , further comprising polishing the first inter-layer dielectric to expose an upper surface of the dielectric etch stop layer.

12. The method of claim 11 , where polishing the first inter-layer dielectric is performed by subjecting the semiconductor memory device to a selective slurry.

13. The method of claim 9 , where etching the semiconductor memory device, to remove a portion of the first inter-layer dielectric in the local interconnect area, further comprises:

etching the first inter-layer dielectric within the local interconnect area using a first etch chemistry; and

etching the dielectric stop layer and dielectric liner layer using a second etch chemistry.

14. A method of fabricating a semiconductor device having a pair of select transistors formed over a substrate, the method comprising:

forming a source region between the pair of select transistors, the source region have a silicide region formed in an upper surface thereof;

forming a liner oxide layer over the pair of select transistors and the source region;

forming spacers adjacent the interior sidewalls of the pair of select transistors over the liner oxide layer;

depositing a inter-layer dielectric between the spacers;

etching the inter-layer dielectric and the liner oxide layer to form an interconnect area have a width less than a distance between the pair of select transistors; and

forming a metal contact within the interconnect area.

15. The method of claim 14 , where the width of the interconnect area is between 40 and 60 nm less than a distance between the pair of source select transistors.

16. The method of claim 14 , further comprising forming at least one of the pair of source select transistors, the forming comprising:

forming a first dielectric layer on the substrate,

forming a charge storage layer on the first dielectric layer,

forming a second dielectric layer on the charge storage layer, and

forming a control gate layer on the second dielectric layer.

17. A method comprising:

forming a pair of source select transistors on a substrate of a semiconductor memory device;

forming a source region in the substrate between the pair of source select transistors;

forming a first inter-layer dielectric between the pair of source select transistors;

depositing a mask layer over the pair of source select transistors and the first inter-layer dielectric,

where the mask layer defines a local interconnect area between the pair of source select transistors having a width less than a distance between the pair of source select transistors;

etching the semiconductor memory device to remove a portion of the first inter-layer dielectric in the local interconnect area, thereby exposing the source region;

forming a barrier metal layer in the local interconnect area prior to forming a metal contact; and

forming the metal contact in the local interconnect area.

18. The method of claim 17 , further comprising, prior to forming the first inter-layer dielectric:

forming a dielectric liner layer over the substrate and the pair of source select transistors; and

forming a spacer layer over the dielectric liner layer,

where the spacer layer is etched to expose at least a portion of the dielectric liner layer over the source region.

19. The method of claim 18 , further comprising forming a dielectric etch stop layer over the spacer layer and the dielectric liner layer prior to forming the first inter-layer dielectric.

20. The method of claim 17 , where

the barrier metal layer is one of titanium layer followed by a titanium nitride layer, each layer having a thickness ranging from about 50 Å to about 300 Å; and

the metal contact comprises tungsten,

where the metal contact is polished to form a tungsten strap.

Assignments (9)