Memory cells with lower power consumption during a write operation
View Patent ↗A memory cell including an access transistor coupled to a first storage node and a read port coupled to one of the first storage node or a second storage node is provided. The memory cell further includes a first inverter having an input terminal coupled to the first storage node, an output terminal, and a first power supply voltage terminal for receiving a first power supply voltage. The memory cell further includes a second inverter having an input terminal coupled to the output terminal of the first inverter, an output terminal coupled to the input terminal of the first inverter at the first storage node, and a second power supply voltage terminal for receiving a second power supply voltage, wherein the second power supply voltage is varied relative to the first power supply voltage during a write operation to the memory cell.
1. A memory cell, comprising:
a first and a second storage node;
an access transistor coupled to the first storage node;
a read port coupled to one of the first or the second storage nodes;
a first inverter having an input terminal coupled to the first storage node, an output terminal, and a first power supply voltage terminal for receiving a first power supply voltage; and
a second inverter having an input terminal coupled to the output terminal of the first inverter, an output terminal coupled to the input terminal of the first inverter at the first storage node, and a second power supply voltage terminal for receiving a second power supply voltage that is not supplied to the first inverter, wherein the second power supply voltage is varied relative to the first power supply voltage during a write operation to the memory cell.
2. The memory cell of claim 1 , wherein during the write operation, the second power supply voltage is lower than the first power supply voltage.
3. The memory cell of claim 1 , wherein the read port comprises:
a first transistor having a first current electrode coupled to a ground terminal, a control electrode coupled to the first storage node, and a second current electrode; and
a second transistor having a first current electrode coupled to the second current electrode of the first transistor, a control electrode coupled to a read word line, and a second current electrode coupled to a read bit line.
4. The memory cell of claim 1 , wherein the second inverter further comprises a third power supply voltage terminal for receiving a third power supply voltage, wherein one of the second power supply voltage or the third power supply voltage is varied during the write operation.
5. The memory cell of claim 1 , wherein the second inverter further comprises a third power supply voltage terminal for receiving a third power supply voltage, wherein during the write operation the second power supply voltage is raised and the third power supply voltage is lowered.
6. The memory cell of claim 1 , wherein the first inverter comprises:
a first transistor having a first current electrode coupled to the first power supply voltage terminal, a control electrode coupled to the first storage node, and a second current electrode coupled to the second storage node; and
a second transistor having a first current electrode coupled to the second current electrode of the first transistor, a control electrode coupled to the control electrode of the first transistor, and a second current electrode coupled to a ground terminal.
7. The memory cell of claim 6 , wherein the second inverter comprises:
a third transistor having a first current electrode coupled to the second power supply voltage terminal, a control electrode coupled to the second storage node, and a second current electrode coupled to the first storage node; and
a fourth transistor having a first current electrode coupled to the second current electrode of the third transistor, a control electrode coupled to the control electrode of the third transistor, and a second current electrode coupled to a third power supply voltage terminal for receiving a third power supply voltage, wherein during a write operation, one of the second or third power supply voltages varied.
8. The memory cell of claim 1 , wherein the access transistor is characterized as being a P-channel transistor.
9. A memory array, comprising:
a plurality of memory cells organized in row and columns, wherein a row of memory cells comprises a word line and all of the memory cells coupled to the word line, wherein a column of memory cells comprises a bit line and all of the memory cells coupled to the bit line; and wherein each of the memory cells comprises:
a first inverter having an input terminal coupled to a first storage node, an output terminal coupled to a second storage node, a first power supply voltage terminal for receiving a first power supply voltage, and a ground terminal;
a second inverter having an input terminal coupled to the output terminal of the first inverter at the second storage node, an output terminal coupled to the input terminal of the first inverter at the first storage node, a second power supply voltage terminal, and a third power supply voltage terminal; and
a read port coupled to one of the first or the second storage nodes;
a first power supply conductor, coupled to the second power supply voltage terminals of each of the plurality of memory cells in a column of memory cells, the first power supply conductor traversing the memory array in a direction parallel to the column of memory cells; and
a second power supply conductor, coupled to the third power supply voltage terminals of each of the plurality of memory cells in a row of memory cells, the second power supply conductor traversing the memory array in a direction parallel to the row of memory cells, wherein both of the second and third power supply voltage terminals receive power supply voltages that are independently variable with respect to the first power supply voltage during a write operation to each of the plurality of memory cells.
10. The memory array of claim 9 , wherein during a write operation, a voltage measured between the second and third power supply voltage terminals is lower than a voltage measured between the first power supply voltage terminal and the ground terminal.
11. The memory array of claim 9 , wherein the read port comprises:
a first transistor having a first current electrode coupled to the ground terminal, a control electrode coupled to the first storage node, and a second current electrode; and
a second transistor having a first current electrode coupled to the second current electrode of the first transistor, a control electrode coupled to a read word line, and a second current electrode coupled to a read bit line.
12. The memory array of claim 9 , wherein the first inverter comprises:
a first transistor having a first current electrode coupled to the first power supply voltage terminal, a control electrode coupled to the first storage node, and a second current electrode coupled to the second storage node; and
a second transistor having a first current electrode coupled to the second current electrode of the first transistor, a control electrode coupled to the control electrode of the first transistor, and a second current electrode coupled to the ground terminal.
13. The memory array of claim 12 , wherein the second inverter comprises:
a third transistor having a first current electrode coupled to the second power supply voltage terminal, a control electrode coupled to the second storage node, and a second current electrode coupled to the second storage node; and
a fourth transistor having a first current electrode coupled to the second current electrode of the third transistor, a control electrode coupled to the control electrode of the third transistor, and a second current electrode coupled to the third power supply voltage terminal.
14. A method for writing to a memory cell, the memory cell comprising a first inverter and a second inverter, the first inverter having an input terminal coupled to a first storage node and an output terminal coupled to a second storage node, the second inverter having an input terminal coupled to the second storage node and an output terminal coupled to the first storage node, the method comprising:
providing a first power supply voltage at a first potential to a first power supply voltage terminal of the second inverter;
providing a second power supply voltage at a second potential to a second power supply voltage terminal of the second inverter;
lowering the first power supply voltage;
raising the second power supply voltage;
coupling the first storage node to a bit line;
returning the first power supply voltage to the first potential;
returning the second power supply voltage to the second potential; and
decoupling the first storage node from the bit line.
15. The method of claim 14 , further comprising providing a read port coupled to one of the first or second storage nodes.
16. A method for writing to a memory cell, the memory cell comprising a first inverter and a second inverter, the first inverter having an input terminal coupled to a first storage node and an output terminal coupled to a second storage node, the second inverter having an input terminal coupled to the second storage node and an output terminal coupled to the first storage node, a read port coupled to one of the first or second storage nodes, the method comprising:
providing a first power supply voltage at a first potential to a first power supply voltage terminal of the second inverter;
providing a second power supply voltage at a second potential to a second power supply voltage terminal of the second inverter but not to the first inverter;
lowering the first power supply voltage;
coupling the first storage node to a bit line;
returning the first power supply voltage to the first potential; and
decoupling the first storage node from the bit line.
17. The method of claim 16 , wherein lowering the first power supply voltage further comprises raising the second power supply voltage and wherein returning the first power supply voltage to the first potential further comprises returning the second power supply voltage to the second potential.
18. The method of claim 16 , wherein coupling the first storage node to the bit line further comprises coupling the first storage node to the bit line using a P-channel transistor.