IP Library Granted Patent US 7,379,360
Granted Patent B1
US 7,379,360 · App. 11/616,702 · Granted May 27, 2008

Repair fuse circuit for storing I/O repair information therein

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Quick Facts
Patent No.
US 7,379,360
App. No.
11/616,702
Granted
May 27, 2008
Kind
B1
Abstract

A repair fuse circuit includes an address comparator, and a plurality of I/O bus select bit output units. The address comparator outputs repair signals for selecting a redundant column that will replace a full column of a plurality of redundant columns according to a column address. The plurality of I/O bus select bit output units for outputting signals corresponding to respective bits of I/O bus repair signals for selecting an I/O bus to which the redundant column will be connected according to the repair signals.

Claims (16)

1. A repair fuse circuit, comprising:

an address comparator to output repair signals for selecting a redundant column according to a column address, the redundant column being selected to replace a fail column and selected from a plurality of redundant columns; and

a plurality of I/O bus select bit output units to output signals corresponding to respective bits of I/O bus repair signals for selecting an I/O bus to which the redundant column is to be connected according to the repair signals.

2. The repair fuse circuit of claim 1 , wherein the address comparator outputs the repair signals corresponding to the redundant columns.

3. The repair fuse circuit of claim 2 , wherein the address comparator outputs a repair signal to select a redundant column that is to replace the fail column of the redundant columns, wherein the repair signal output to select the redundant column has a different logic level than remaining repair signals.

4. The repair fuse circuit of claim 1 , wherein a bit number of the I/O bus repair signal is the same as the number of the I/O bus select bit output unit.

5. The repair fuse circuit of claim 1 , wherein the I/O bus select bit output unit comprises:

a plurality of a switching elements operating according to the repair signals, respectively, and connected to a ground terminal in parallel;

a transistor connected to a power supply voltage terminal;

fuses, each connected between the transistor and one of the switching elements; and

an inverter to invert a voltage level of a node between the transistor and the fuses and apply the voltage level to a gate of the transistor.

6. The repair fuse circuit of claim 5 , wherein the fuses are installed as many as the number of redundant columns.

7. The repair fuse circuit of claim 5 , wherein an I/O bus to which a n th redundant column is to be connected is decided according to a cutting state of a n th fuse of the fuses.

8. The repair fuse circuit of claim 5 , further comprising a buffer connected to an output terminal of the inverter.

9. The repair fuse circuit of claim 5 , wherein the switching element comprises a NMOS transistor.

10. The repair fuse circuit of claim 5 , wherein the transistor comprises a PMOS transistor.

Assignments (3)
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE IS HYNIX SEMICONDUCTOR INC. NOT HYNIX-SEMICONDUCTOR INC. THERE IS NO HYPHEN IN THE NAME. PREVIOUSLY RECORDED ON REEL 67328 FRAME 814. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME. Recorded May 14, 2024
From: HYNIX SEMICONDUCTOR INC.
To: SK HYNIX INC.
Reel/Frame 067412/0482 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 9, 2024
From: SK HYNIX INC.
To: MIMIRIP LLC
Reel/Frame 067369/0832 →
CHANGE OF NAME Recorded May 6, 2024
From: HYNIX-SEMICONDUCTOR INC.
To: SK HYNIX INC.
Reel/Frame 067328/0814 →