Method of fabricating a semiconductor device
View Patent ↗Embodiments relate to a method for fabricating a semiconductor device. In embodiments, the method may include forming a gate dielectric layer on an active region of a semiconductor substrate defined by an isolation region to form a gate conductive layer pattern, etching the isolation region of the semiconductor substrate where the gate conductive layer pattern is formed, to form an isolation trench, forming a polyoxide layer on the gate conductive layer pattern and a sidewall oxide layer in the trench by carrying out an oxidation process, forming a spacer nitride layer on the polyoxide layer and a liner nitride layer on the sidewall oxide layer by carrying out a nitride layer forming process, and then forming a dielectric layer on an entire surface of the resultant structure to fill the trench.
1. A method comprising:
forming a gate conductive layer pattern over an active region of a semiconductor substrate defined by an isolation region;
forming an isolation trench by etching the isolation region of the semiconductor substrate;
forming a polyoxide layer over the gate conductive layer pattern and a sidewall oxide layer over a sidewall in the trench by performing an oxidation process; and
forming a spacer nitride layer over the polyoxide layer and a liner nitride layer over the sidewall oxide layer by performing a nitride layer forming process,
wherein the polyoxide layer and the sidewall oxide layer are formed in a single oxidation process and the spacer nitride layer and the liner nitride layer are formed in a single nitride layer forming process.
2. The method of claim 1 , further comprising forming a dielectric layer over an entire surface of the resultant structure to fill the trench.
3. The method of claim 1 , wherein a gate dielectric layer is provided over the entire semiconductor substrate prior to forming the isolation trench.
4. The method of claim 1 , wherein forming the gate conductive layer pattern comprises:
sequentially depositing a gate dielectric layer and a gate conductive layer over the semiconductor substrate;
forming a photoresist layer pattern over the gate conductive layer;
removing an exposed portion of the gate conductive layer by an etching process using the photoresist layer pattern as an etching mask, thereby forming the gate conductive layer pattern; and
removing the photoresist layer pattern.
5. The method of claim 4 , wherein the gate conductive layer pattern comprises at least one gate electrode.
6. The method of claim 1 , wherein forming the isolation trench comprises:
forming a photoresist layer pattern to expose the isolation region of the semiconductor substrate while not exposing the conductive layer pattern;
etching the isolation region of the semiconductor substrate to a prescribed depth by an etching process using the photoresist layer pattern as an etching mask; and
removing the photoresist layer pattern.
7. The method of claim 6 , wherein the exposed isolation region of the semiconductor substrate comprises a gate dielectric layer formed over the semiconductor substrate, and wherein the exposed portion of the gate dielectric layer and the semiconductor substrate are etched using the photoresist layer pattern as an etching mask.
8. The method of claim 1 , wherein the gate conductive layer pattern comprises a polysilicon layer.
9. A method comprising:
forming a gate conductive layer pattern over an active region of a semiconductor substrate defined by an isolation region;
forming an isolation trench in the isolation region after forming the gate conductive layer pattern;
simultaneously forming a polyoxide layer over the gate conductive layer pattern and a sidewall oxide layer in the trench by performing a single oxidation process after forming the isolation trench and the gate conductive layer pattern; and
simultaneously forming a spacer nitride layer over the polyoxide layer and a liner nitride layer over the oxide layer by performing a single nitride layer forming process.
10. The method of claim 9 , wherein the gate conductive layer pattern comprises a polysilicon layer.
11. The method of claim 10 , further comprising, after forming the isolation trench and before simultaneously forming the polyoxide layer over the gate conductive layer pattern and the sidewall oxide layer in the trench:
forming a dielectric layer over an entire surface of the resultant structure to fill the trench.
12. The method of claim 9 , wherein forming the isolation trench comprises:
forming a photoresist layer pattern to expose the isolation region of the semiconductor substrate while not exposing the conductive layer pattern;
etching the isolation region of the semiconductor substrate to a prescribed depth by an etching process using the photoresist layer pattern as an etching mask; and then
removing the photoresist layer pattern.
13. The method of claim 9 , wherein forming the gate conductive layer pattern comprises:
sequentially depositing a gate dielectric layer and a gate conductive layer over the semiconductor substrate;
forming a photoresist layer pattern over the gate conductive layer;
removing an exposed portion of the gate conductive layer by an etching process using the photoresist layer pattern as an etching mask, thereby forming the gate conductive layer pattern; and then
removing the photoresist layer pattern.