Semiconductor device
View Patent ↗Embodiments relate to a semiconductor device and a method of fabricating semiconductor device, that may uniformly form a barrier layer in a via hole to thus prevent layers from being broken. In embodiments, a method of fabricating a semiconductor device may include forming an interlayer dielectric layer on a substrate, forming via holes selectively on the interlayer dielectric layer, forming a first metal layer on a top surface of the substrate including inner portion of the via hole, forming spacers on sides of the via holes by etching back the first metal layer, forming a second metal layer on the substrate including the spacer, and forming a tungsten layer by depositing tungsten on the second metal layer.
1. A method comprising:
forming a first metal layer over a substrate;
forming an interlayer dielectric layer over the substrate including the first metal layer;
forming a via hole in the interlayer dielectric layer exposing the first metal layer;
forming a second metal layer in the via hole on sidewalls of the interlayer dielectric layer;
forming spacers in the via hole and contacting at least a portion of the exposed first metal layer by etching back the second metal layer exposing a portion of the sidewalls of the interlayer dielectric layer;
forming a third metal layer over the spacers and the exposed portion of the sidewalls of the interlayer dielectric layer and the exposed first metal layer; and
forming a fourth metal layer by depositing a conductive metal over the third metal layer to fill the via hole.
2. The method of claim 1 , wherein the fourth metal layer comprises tungsten.
3. The method of claim 1 , further comprising planarizing the substrate having the fourth metal layer through chemical mechanical polishing.
4. The method of claim 1 , wherein a thickness of the spacers is 50 Å or less.
5. The method of claim 1 , wherein a thickness of the third metal layer is no more than half of a thickness of the second metal layer.
6. The method of claim 1 , wherein a thickness of the third metal layer is in a range of 100 Å to 350 Å.
7. The method of claim 1 , wherein the etching-back of the second metal layer is performed by injecting approximately 120 sccm of SF 6 and approximately 120 sccm of Ar.
8. The method of claim 1 , wherein the third metal layer is formed through chemical vapor deposition.
9. The method of claim 1 , wherein a thickness of the second metal layer is greater than a thickness of the third metal layer.
10. The method of claim 1 , wherein the second metal layer comprises a material identical to a material forming the third metal layer.
11. A method comprising:
forming an interlayer dielectric layer including a via hole over a semiconductor subtrate;
depositing a first metal layer in the via hole and on sidewalls of the interlayer dielectric layer;
forming spacers in the via hole and covering a lower portion of the sidewalls of the interlayer dielectric layer by etching back the first metal layer exposing a portion of the sidewalls of the interlayer dielectric layer;
forming a second metal layer over the spacers and the exposed portion of the sidewalls of the interlayer dielectric layer, thereby forming a barrier layer comprising the first and second metal layers; and
filling at least an inner portion of the via hole with a conductive material.
12. The method of claim 11 , wherein the conductive material comprises tungsten.
13. The method of claim 11 , wherein the barrier layer comprises at least one of Ti, TiN, Ti/TiN, and Ti/Al/Ti.
14. The method of claim 11 , further comprising, before forming the interlayer dielectric layer; forming a third metal layer on the semiconductor substrate, wherein forming the via hole is performed by selectively etching the interlayer dielectric, to expose the third metal layer.
15. A device comprising:
a first metal layer formed over a substrate;
an insulating layer formed on the first metal layer;
via holes formed in the insulating layer exposing the first metal layer; and
a barrier layer formed in the via hole, wherein the barrier layer comprises:
spacers including a second metal layer formed in the via hole and in contact with a portion of the insulating layer and the exposed first metal layer; and
a third metal layer formed in the via hole and over the first and second metal layers.
16. The device of claim 15 , further comprising a conductive material formed over the barrier layer, wherein the conductive material comprises tungsten.
17. The device of claim 16 , wherein the conductive material is deposited through chemical vapor deposition.
18. The device of claim 15 , wherein a thickness of the lower edge of the barrier layer is greater than a thickness of the upper edge of the barrier layer.
19. The device of claim 15 , wherein a thickness of the spacers is 50 Å or less.
20. The device of claim 15 , wherein a thickness of the second metal layer is in a range of 100 Å to 350 Å.
21. The device of claim 15 , wherein the spacers comprise a material identical to a material forming the second metal layer.