Methods of manufacturing a three-dimensional semiconductor device and semiconductor devices fabricated thereby
A method of fabricating a three-dimensional semiconductor device is provided along with a three-dimensional semiconductor device fabricated thereby. The method includes forming a heat conductive plug to channel heat away from devices on a substrate, while high temperature processes are performed on a stacked semiconductor layer. The ability to use high temperature processes on the stacked semiconductor layer without adversely effecting devices on the substrate allows the formation of a high quality single-crystalline stacked semiconductor layer. The high quality single-crystalline semiconductor layer can then be used to fabricate improved thin film transistors.
1. A method of manufacturing a semiconductor device comprising:
forming an insulation layer on a first semiconductor substrate;
forming an opening through the insulation layer, the opening exposing a region of the first semiconductor substrate;
forming a heat conductive plug in the opening;
forming a separation layer in a second semiconductor substrate, the separation layer separating a surface layer and a bulk layer on the second semiconductor substrate;
bonding the insulation layer of the first substrate to the surface layer of the second substrate;
delaminating the bulk layer from the surface layer at the separation layer;
heat treating the surface layer while conducting heat away from the surface layer primarily through the heat conductive plug into the first semiconductor substrate; and
forming an upper device on the surface layer.
2. The method of claim 1 , wherein the heat conductive plug has a higher heat conductivity than the insulation layer.
3. The method of claim 1 , wherein forming the insulation layer on the first semiconductor substrate comprises:
forming a lower discrete device on the first semiconductor substrate; and
forming the insulation layer on the first semiconductor substrate substantially covering the lower device.
4. The method of claim 3 , wherein forming a lower discrete device comprises forming a bulk transistor.
5. The method of claim 1 , wherein forming the separation layer comprises implantation of impurity ions into the first semiconductor substrate.
6. The method of claim 5 , wherein the impurity ions are hydrogen ions.
7. The method of claim 6 , wherein the hydrogen ions are implanted with a dose of about 1×10 16 atoms/cm 2 to about 1×10 17 atoms/cm 2 .
8. The method of claim 1 , further comprising creating a hydrophilic surface on the insulation layer and the surface layer.
9. The method of claim 8 , wherein creating a hydrophilic surface comprises exposing the insulation layer and the surface layer to a plasma including a plasma source gas.
10. The method of claim 9 , wherein the plasma source gas is oxygen gas.
11. The method of claim 8 , wherein creating a hydrophilic surface comprises:
cleaning the insulation layer and the surface layer using a wet process; and
exposing the insulation layer and the surface layer to hydrofluoric acid.
12. The method of claim 1 , wherein bonding the insulation layer to the surface layer comprises:
placing the insulation layer in contact with the surface layer; and
heating the insulation layer and surface layer at a temperature of about 100° C. to about 600° C.
13. The method of claim 1 , wherein delaminating the bulk layer from the surface layer comprises:
heating the separation layer at a temperature of about 200° C. to about 900° C.; and
removing the separation layer and the bulk layer from the surface layer.
14. The method of claim 13 , wherein heating the separation layer is performed in a nitrogen environment.
15. The method of claim 1 , wherein heat treating the surface layer is performed at a temperature of about 600° C. to about 1200° C.
16. The method of claim 1 , further comprising, after delaminating:
blanket etching the surface layer.
17. The method of claim 16 , wherein etching the surface layer comprises a wet etch process, a dry etch process, or a chemical-mechanical polishing (CMP) process.
18. The method of claim 15 , further comprising cooling the first semiconductor substrate while heat treating.
19. The method of claim 18 , wherein cooling comprises placing the first semiconductor substrate in contact with a heat sink.
20. The method of claim 19 , wherein the heat sink comprises a cooling stage having a coolant medium.
21. The method of claim 15 , wherein heat treating the surface layer is performed in an environment comprising nitrogen gas, hydrogen gas, or oxygen gas.
22. The method of claim 15 , wherein heat treating the surface layer comprises placing the surface layer in a furnace, exposing the surface layer with a halogen lamp, or exposing the surface layer with a laser.
23. The method of claim 1 , further comprising, after delaminating:
forming a sacrificial oxide layer on the surface layer; and
removing the sacrificial oxide layer.
24. The method of claim 23 , wherein forming a sacrificial oxide layer is performed at a temperature range of about 500° C. to 1000° C. for a time period of about thirty (30) minutes to four (4) hours.
25. A method of manufacturing a semiconductor device, the method comprising:
forming a lower device in a first region of a first semiconductor substrate;
forming an insulation layer on the first semiconductor substrate, the insulation layer having the lower device therein;
forming an opening through the insulation layer, exposing a second region of the first semiconductor substrate;
forming a heat conductive plug in the opening, the heat conductive plug having a higher heat conductivity than the insulation layer;
forming a separation layer in a second semiconductor substrate, wherein the separation layer separates a surface layer and a bulk layer on the second semiconductor substrate and the surface layer comprises a single-crystalline material;
performing a surface treatment on the insulation layer and the surface layer, wherein the surface treatment creates a hydrophilic surface on the insulation layer and the surface layer;
bonding the insulation layer to the surface layer;
delaminating the bulk layer from the surface layer at the separation layer;
heat treating the surface layer to remove any artifacts of the forming of and delaminating at the separation layer from the surface layer, wherein heat treating comprises:
placing the first semiconductor substrate on a cooling stage; and
applying heat to the surface layer thereby channeling heat away from the surface layer through the heat conductive plug into the first semiconductor substrate toward the cooling stage; and
then, forming an upper device on the surface layer.
26. The method of claim 25 , wherein the second region of the first semiconductor substrate comprises a scribe line area.