Method for manufacturing dynamic random access memory
View Patent ↗The present invention has an object to provide a method for manufacturing a dynamic random access memory capable of reducing a defect rate even if the memory has a large packing density. The method of the present invention is a method for manufacturing a dynamic random access memory having memory array areas and a peripheral circuit area arranged in a semiconductor substrate and a silicon nitride film provided over the memory array areas and the peripheral circuit area, the method having at least a step (1) of eliminating the silicon nitride film provided in the peripheral circuit area; and a step (2) of processing in an atmosphere of a hydrogen gas a substrate-to-be-processed obtained by the step (1).
1. A method for manufacturing a dynamic random access memory having a memory cell array area and a peripheral circuit area arranged along the circumference of the memory cell array area, the method comprising at least:
a step (1) of forming a plurality of first field effect transistors in the memory cell array area and a plurality of second field effect transistors in the peripheral circuit area;
a step (2) of forming a first interlayer insulating layer on a whole surface so as to cover said plurality of the first field effect transistors and said plurality of the second field effect transistors, and flattening the surface of the first interlayer insulating layer;
a step (3) of forming a plurality of cell contacts in the first interlayer insulating layer, each of the cell contacts being electrically connected to an associated one of the first field effect transistors;
a step (4) of forming a second interlayer insulating layer on the plurality of the cell contacts and the first interlayer insulating layer;
a step (5) of forming a plurality of bit contacts penetrating through the second interlayer insulating layer and the first interlayer insulating layer in the peripheral circuit area, each of the bit contacts being electrically connected to an associated gate electrode of each of the second field effect transistors;
a step (6) of forming bit lines on the bit contacts;
a step (7) of forming a third interlayer insulating layer on whole surfaces so as to cover the bit lines, and flattening the surface of the third interlayer insulating layer;
a step (8) of forming a plurality of capacity contacts penetrating through the third interlayer insulating layer and the second interlayer insulating layer in the memory cell array area, each of the capacity contacts being electrically connected to each of the cell contacts;
a step (9) of forming a silicon nitride film on the plurality of the capacity contacts and the third interlayer insulating layer;
a step (10) of eliminating 5 to 90% of the silicon nitride film in the whole surfaces, except for a part of the memory cell array area and a part of the peripheral circuit area where a through hole will be formed;
a step (11) of forming a forth interlayer insulating layer on whole surfaces so as to cover the silicon nitride film and areas where the silicon nitride film has been eliminated;
a step (12) of forming a plurality of cylinder holes penetrating through the forth interlayer insulating layer so as to expose the silicon nitride film on the plurality of the capacity contacts;
a step (13) of exposing the surfaces of the plurality of the capacity contacts by eliminating the silicon nitride film exposing at the bottoms of the cylinder holes;
a step (14) of forming a plurality of capacitors in the cylinder holes, each of capacitors including a lower electrode electrically connected to an associated one of the capacity contacts, a dielectric film formed on the lower electrode and an upper electrode formed on the dielectric film;
a step (15) of forming a fifth interlayer insulating layer on the plurality of the capacitors and the forth interlayer insulating layer;
a step (16) of forming the through holes connected to the bit lines, which penetrate through the fifth interlayer insulating layer, the forth interlayer insulating layer, the silicon nitride film and the third interlayer insulating layer; and
a step (17) of processing the substrate in an atmosphere containing a hydrogen gas after the step (10).
2. The method of claim 1 , wherein in the step (10), 10 to 50% of the silicon nitride film in the whole surfaces are eliminated.
3. The method of claim 1 , wherein in the step (10), 15 to 40% of the silicon nitride film in the whole surfaces are eliminated.
4. A method for manufacturing a dynamic random access memory having a memory cell array area and a peripheral circuit area arranged along the circumference of the memory cell array area, the method comprising at least:
a step (1) of forming a plurality of first field effect transistors in the memory cell array area and a plurality of second field effect transistors in the peripheral circuit area;
a step (2) of forming a first interlayer insulating layer on a whole surface so as to cover said plurality of the first field effect transistors and said plurality of the second field effect transistors, and flattening the surface of the first interlayer insulating layer;
a step (3) of forming a plurality of cell contacts in the first interlayer insulating layer, each of the cell contacts being electrically connected to an associated one of the first field effect transistors;
a step (4) of forming a second interlayer insulating layer on the plurality of the cell contacts and the first interlayer insulating layer;
a step (5) of forming a plurality of bit contacts penetrating through the second interlayer insulating layer and the first interlayer insulating layer in the peripheral circuit area, each of the bit contacts being electrically connected to an associated gate electrode of each of the second field effect transistors;
a step (6) of forming bit lines on the bit contacts;
a step (7) of forming a third interlayer insulating layer on whole surfaces so as to cover the bit lines, and flattening the surface of the third interlayer insulating layer;
a step (8) of forming a plurality of capacity contacts penetrating through the third interlayer insulating layer and the second interlayer insulating layer in the memory cell array area, each of the capacity contacts being electrically connected to each of the cell contacts;
a step (9) of forming a silicon nitride film on the plurality of the capacity contacts and the third interlayer insulating layer;
a step (10) of eliminating 5 to 90% of the silicon nitride film in the whole surfaces, except for a part of the memory cell array area and a part of the peripheral circuit area where a through hole will be formed;
a step (11) of forming a forth interlayer insulating layer on whole surfaces so as to cover the silicon nitride film and areas where the silicon nitride film has been eliminated;
a step (12) of forming a plurality of cylinder holes penetrating through the forth interlayer insulating layer so as to expose the silicon nitride film on the plurality of the capacity contacts;
a step (13) of exposing the surfaces of the plurality of the capacity contacts by eliminating the silicon nitride film exposing at the bottoms of the cylinder holes;
a step (14) of forming a plurality of capacitors in the cylinder holes, each of capacitors including a lower electrode electrically connected to an associated one of the capacity contacts, a dielectric film formed on the lower electrode and an upper electrode formed on the dielectric film;
a step (15) of forming a fifth interlayer insulating layer on the plurality of the capacitors and the forth interlayer insulating layer;
a step (16) of forming the through holes connected to the bit lines, which penetrate through the fifth interlayer insulating layer, the forth interlayer insulating layer, the silicon nitride film and the third interlayer insulating layer; and
a step (17) of processing the substrate in an atmosphere containing a hydrogen gas after the step (10),
wherein the step (17) is performed at a temperature in a range of from 380 to 470° C., and for a time duration of from one-half hour to twelve hours.
5. The method of claim 4 , further comprising:
a step (18) of lowering the temperature to 300° C. or less after the step (17).
6. The method of claim 1 , wherein forming the silicon nitride film of the step (9) is performed at a temperature in the range of from 600 to 650° C.
7. The method of claim 1 , wherein in the step (9), a forming thickness of silicon nitride film is in the range of from 30 to 70 nm.
8. The method of claim 1 , wherein in the step (9), a forming thickness of silicon nitride film is in the range of from 40 to 60 nm.
9. The method of claim 4 , wherein in the step (10), 10 to 50% of the silicon nitride film in the whole surfaces are eliminated.
10. The method of claim 4 , wherein in the step (10), 15 to 40% of the silicon nitride film in the whole surfaces are eliminated.