IP Library Granted Patent US 7,411,806
Granted Patent B2
US 7,411,806 · App. 11/634,405 · Granted Aug 12, 2008

Memory module and memory system

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Quick Facts
Patent No.
US 7,411,806
App. No.
11/634,405
Granted
Aug 12, 2008
Kind
B2
Abstract

A memory module has a plurality of DRAMs ( 115 ), which share a bus line, on the front surface and the back surface of a board. The bus line is connected through a via hole ( 113 ) from a terminal ( 111 ) to one end of a strip line ( 112 ), and the other end of the strip line is connected to a strip line in the other layer through a via hole ( 119 ) provided for looping back the line. A termination resistor ( 120 ), provided near a termination voltage terminal (VTT), is connected to the looped-back strip line in the other layer through a via hole. The DRAM terminals are connected to the strip line each through a via hole. This memory module is mounted on a motherboard, on which a memory controller is provided, through a connector. The effective characteristic impedance of the bus line is matched with the characteristic impedance of the line in the motherboard.

Claims (24)

1. A memory module comprising a board on which a plurality of memory devices, which share a bus line, are mounted on at least one of a front surface and a back surface,

wherein said bus line is connected to one end of a strip line through a via hole on said board,

wherein terminals of said plurality of memory devices on said board are connected to said strip line each through a via hole, and

wherein another end of said strip line is terminated by being connected to a termination circuit on the front surface of the board or the back surface of the board through a via hole or to a terminal of a memory device including a termination circuit.

2. The memory module as defined by claim 1 wherein the terminals of the memory devices on the front surface of the board and the terminals of the memory devices on the back surface of the board are connected alternately to said strip line each through a via hole.

3. A memory module comprising a board on which a plurality of memory devices, which share a bus line, are mounted on a front surface and a back surface,

wherein said bus line is extended on the front surface of said board from a first module terminal to a via hole spaced from said first module terminal and is connected to one end of a strip line through the via hole and the other end of said strip line is connected through a via hole to a termination circuit provided on the front surface or back surface of the board and

wherein, for each of two memory devices mounted in opposing positions on the front surface and back surface of the board, said strip line is connected to terminals of said two memory devices each through a via hole extended from one position on said strip line to the front surface and the back surface.

4. The memory module as defined by claim 1 wherein said strip line is terminated by being connected to the terminal of the memory device including the termination circuit.

5. The memory module as defined by claim 1 , wherein said strip line is within the board.

6. The memory module as defined by claim 3 wherein:

the termination circuit is included in at least one of said plurality of memory devices, and

the memory device in which said termination circuit is included terminates the end of said bus line.

7. The memory module as defined by claim 3 , wherein said strip line is within the board.

8. A memory module comprising:

a board;

a plurality of memory devices mounted on a first side of the board; and

a bus line shared by the plurality of memory devices and mounted on at least one of the front side and a back side of the board, the bus line being connected to one end of a strip line;

wherein another end of the strip line is terminated by being connected to a memory device including a termination circuit.

9. The memory module as defined by claim 8 , wherein the termination circuit is mounted on the front side.

10. The memory module as defined by claim 8 , wherein the termination circuit is mounted on the back side and connects to the strip line through a via hole.

11. The memory module as defined by claim 8 , wherein the bus line is connected to the one end of the strip line through a via hole on the board.

12. The memory module as defined by claim 8 , wherein terminals of the plurality of memory devices on the board are connected to the strip line each through respective via holes.

13. The memory module defined by claim 8 , wherein said strip line is within the board.

Assignments (7)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 21, 2018
From: LONGITUDE SEMICONDUCTOR S.A.R.L.
To: LONGITUDE LICENSING LIMITED
Reel/Frame 046867/0248 →
CHANGE OF NAME Recorded Aug 24, 2016
From: PS5 LUXCO S.A.R.L.
To: LONGITUDE SEMICONDUCTOR S.A.R.L.
Reel/Frame 039793/0880 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 24, 2016
From: PS4 LUXCO S.A.R.L.
To: PS5 LUXCO S.A.R.L.
Reel/Frame 039818/0506 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 15, 2014
From: ELPIDA MEMORY, INC.
To: PS4 LUXCO S.A.R.L.
Reel/Frame 032895/0310 →
RELEASE OF SECURITY INTEREST Recorded Feb 24, 2014
From: APPLE, INC
To: ELPIDA MEMORY, INC.
Reel/Frame 032331/0637 →
SECURITY AGREEMENT Recorded Jul 29, 2013
From: PS4 LUXCO S.A.R.L.
To: ELPIDA MEMORY INC.
Reel/Frame 032414/0261 →
SECURITY AGREEMENT Recorded May 15, 2012
From: ELPIDA MEMORY, INC.
To: APPLE INC.
Reel/Frame 028209/0477 →