Optimization of flip flop initialization structures with respect to design size and design closure effort from RTL to netlist
View Patent ↗A method for optimizing a design of a circuit is disclosed. The method generally includes the steps of (A) identifying a plurality of first flip flops in the design and (B) replacing each of the first flip flops in a file of the design that do not have to be initialized during operations of the circuit with a respective second flip flop without an initialization capability.
1. A method for optimizing a design of a circuit, comprising steps of:
(A) identifying a plurality of first flip flops in a first version of said design using a computer program;
(B) creating a second version of said design by replacing each of said first flip flops in a file of said design that do not have to be initialized during operations of said circuit with a respective second flip flop without an initialization capability; and
(C) generating a plurality of commands suitable to use in a verification tool, said verification tool being configured to perform a comparison of said first version of said design against said second version of said design, and said commands instructing said verification tool to ignore one or more nets related to initialization of said first flip flops that have been replaced by said second flip flops in said comparison.
2. The method according to claim 1 , further comprising a step of:
comparing said first flip flops against a plurality of rules to determined which of said first flip flops do not have to be initialized during said operations.
3. The method according to claim 1 , further comprising a step of:
removing from said file of said design a respective initialization circuit for each of said first flip flops replaced by said respective second flip flops.
4. The method according to claim 1 , wherein said design comprises a netlist for said circuit.
5. The method according to claim 1 , wherein said design comprises a register transfer language code for said circuit.
6. The method according to claim 1 , wherein said respective second flip flops have (i) a smaller physical area, (ii) a lower gate count and (iii) fewer nets to route than said first flip flops.
7. The method according to claim 1 , for implementing a storage medium storing said computer program comprising the steps of claim 1 .
8. The method according to claim 1 , further comprising a step of:
generating a respective command to initialize said respective second flip flops in a simulation.
9. The method according to claim 1 , further comprising a step of:
marking each of said second flip flops of said design with a respective static timing analysis constraint.
10. A method for optimizing a design of a circuit, comprising steps of:
(A) analyzing a first version of said design to create a set of first flip flops that have an initialization capability using a computer program;
(B) eliminating from said set each of said first flip flops that has to be initialized;
(C) creating a second version of said design by modifying a file of said design to replace each of said first flip flops remaining in said set with a respective second flip flop that lacks said initialization capability; and
(D) generating a plurality of commands suitable to use in a simulation tool, said simulation tool being configured to perform a simulation of said second version of said design, said commands instructing said simulation tool how and when to force each of said second flip flops to a respective one of a plurality of initial values during said simulation, and said initial values matching a plurality of initialization conditions of said first flip flops that were replaced in said first design.
11. The method according to claim 10 , wherein step (B) comprises a sub-step of:
comparing said first flip flops against a plurality of rules to determine which of said first flip flops have to be initialized.
12. The method according to claim 11 , wherein said comparing of said first flip flops against said rules is performed sequentially, one of said first flip flops at a time.
13. The method according to claim 11 , further comprising a step of:
maintaining said first flip flops in said file that have to be initialized according to said rules.
14. The method according to claim 10 , further comprising a step of:
generating a plurality of scripts for verifying said design after modification with said respective second flip flops.
15. The method according to claim 10 , further comprising a step of:
removing from said file a respective initialization circuit for each of said first flip flops replaced by said respective second flip flops.
16. The method according to claim 10 , for implementing a storage medium storing said computer program comprising the steps of claim 10 .
17. The method according to claim 10 , further comprising a step of:
marking each of said second flip flops of said design with a respective static timing analysis constraint.
18. A method for optimizing a design of a circuit, comprising steps of:
(A) generating a list of one or more flip flops in said design having an initialization capability using a computer program;
(B) eliminating from said list each of said flip flops that have to be initialized; and
(C) marking in a file a respective static timing analysis constraint for each of said flip flops remaining in said list.
19. The method according to claim 18 , wherein said respective static timing analysis constraints exempt said flip flops in said list from a timing closure analysis.
20. The method according to claim 18 , wherein step (B) comprises a sub-step of:
comparing said flip flops against a plurality of rules to determined which of said flip flops do not have to be initialized during operations of said circuit.
21. The method according to claim 20 , wherein said rules are variable by a user.
22. The method according to claim 18 , for implementing a storage medium storing said computer program comprising the steps of claim 18 .